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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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dd113c4fef
Document the device tree bindings of the rockchip rk3562 SoC clock and reset unit. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org> Link: https://lore.kernel.org/r/20250227105916.2340856-2-kever.yang@rock-chips.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
380 lines
9.8 KiB
C
380 lines
9.8 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2022-2025 Rockchip Electronics Co., Ltd.
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* Author: Finley Xiao <finley.xiao@rock-chips.com>
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*/
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#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3562_H
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#define _DT_BINDINGS_CLK_ROCKCHIP_RK3562_H
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/* cru-clocks indices */
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/* cru plls */
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#define PLL_DMPLL0 0
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#define PLL_APLL 1
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#define PLL_GPLL 2
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#define PLL_VPLL 3
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#define PLL_HPLL 4
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#define PLL_CPLL 5
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#define PLL_DPLL 6
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#define PLL_DMPLL1 7
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/* cru clocks */
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#define ARMCLK 8
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#define CLK_GPU 9
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#define ACLK_RKNN 10
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#define CLK_DDR 11
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#define CLK_MATRIX_50M_SRC 12
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#define CLK_MATRIX_100M_SRC 13
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#define CLK_MATRIX_125M_SRC 14
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#define CLK_MATRIX_200M_SRC 15
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#define CLK_MATRIX_300M_SRC 16
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#define ACLK_TOP 17
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#define ACLK_TOP_VIO 18
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#define CLK_CAM0_OUT2IO 19
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#define CLK_CAM1_OUT2IO 20
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#define CLK_CAM2_OUT2IO 21
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#define CLK_CAM3_OUT2IO 22
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#define ACLK_BUS 23
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#define HCLK_BUS 24
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#define PCLK_BUS 25
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#define PCLK_I2C1 26
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#define PCLK_I2C2 27
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#define PCLK_I2C3 28
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#define PCLK_I2C4 29
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#define PCLK_I2C5 30
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#define CLK_I2C 31
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#define CLK_I2C1 32
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#define CLK_I2C2 33
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#define CLK_I2C3 34
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#define CLK_I2C4 35
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#define CLK_I2C5 36
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#define DCLK_BUS_GPIO 37
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#define DCLK_BUS_GPIO3 38
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#define DCLK_BUS_GPIO4 39
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#define PCLK_TIMER 40
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#define CLK_TIMER0 41
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#define CLK_TIMER1 42
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#define CLK_TIMER2 43
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#define CLK_TIMER3 44
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#define CLK_TIMER4 45
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#define CLK_TIMER5 46
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#define PCLK_STIMER 47
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#define CLK_STIMER0 48
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#define CLK_STIMER1 49
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#define PCLK_WDTNS 50
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#define CLK_WDTNS 51
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#define PCLK_GRF 52
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#define PCLK_SGRF 53
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#define PCLK_MAILBOX 54
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#define PCLK_INTC 55
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#define ACLK_BUS_GIC400 56
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#define ACLK_BUS_SPINLOCK 57
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#define ACLK_DCF 58
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#define PCLK_DCF 59
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#define FCLK_BUS_CM0_CORE 60
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#define CLK_BUS_CM0_RTC 61
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#define HCLK_ICACHE 62
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#define HCLK_DCACHE 63
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#define PCLK_TSADC 64
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#define CLK_TSADC 65
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#define CLK_TSADC_TSEN 66
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#define PCLK_DFT2APB 67
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#define CLK_SARADC_VCCIO156 68
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#define PCLK_GMAC 69
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#define ACLK_GMAC 70
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#define CLK_GMAC_125M_CRU_I 71
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#define CLK_GMAC_50M_CRU_I 72
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#define CLK_GMAC_50M_O 73
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#define CLK_GMAC_ETH_OUT2IO 74
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#define PCLK_APB2ASB_VCCIO156 75
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#define PCLK_TO_VCCIO156 76
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#define PCLK_DSIPHY 77
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#define PCLK_DSITX 78
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#define PCLK_CPU_EMA_DET 79
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#define PCLK_HASH 80
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#define PCLK_TOPCRU 81
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#define PCLK_ASB2APB_VCCIO156 82
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#define PCLK_IOC_VCCIO156 83
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#define PCLK_GPIO3_VCCIO156 84
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#define PCLK_GPIO4_VCCIO156 85
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#define PCLK_SARADC_VCCIO156 86
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#define PCLK_MAC100 87
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#define ACLK_MAC100 89
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#define CLK_MAC100_50M_MATRIX 90
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#define HCLK_CORE 91
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#define PCLK_DDR 92
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#define CLK_MSCH_BRG_BIU 93
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#define PCLK_DDR_HWLP 94
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#define PCLK_DDR_UPCTL 95
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#define PCLK_DDR_PHY 96
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#define PCLK_DDR_DFICTL 97
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#define PCLK_DDR_DMA2DDR 98
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#define PCLK_DDR_MON 99
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#define TMCLK_DDR_MON 100
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#define PCLK_DDR_GRF 101
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#define PCLK_DDR_CRU 102
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#define PCLK_SUBDDR_CRU 103
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#define CLK_GPU_PRE 104
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#define ACLK_GPU_PRE 105
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#define CLK_GPU_BRG 107
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#define CLK_NPU_PRE 108
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#define HCLK_NPU_PRE 109
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#define HCLK_RKNN 111
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#define ACLK_PERI 112
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#define HCLK_PERI 113
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#define PCLK_PERI 114
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#define PCLK_PERICRU 115
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#define HCLK_SAI0 116
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#define CLK_SAI0_SRC 117
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#define CLK_SAI0_FRAC 118
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#define CLK_SAI0 119
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#define MCLK_SAI0 120
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#define MCLK_SAI0_OUT2IO 121
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#define HCLK_SAI1 122
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#define CLK_SAI1_SRC 123
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#define CLK_SAI1_FRAC 124
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#define CLK_SAI1 125
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#define MCLK_SAI1 126
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#define MCLK_SAI1_OUT2IO 127
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#define HCLK_SAI2 128
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#define CLK_SAI2_SRC 129
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#define CLK_SAI2_FRAC 130
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#define CLK_SAI2 131
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#define MCLK_SAI2 132
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#define MCLK_SAI2_OUT2IO 133
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#define HCLK_DSM 134
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#define CLK_DSM 135
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#define HCLK_PDM 136
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#define MCLK_PDM 137
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#define HCLK_SPDIF 138
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#define CLK_SPDIF_SRC 139
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#define CLK_SPDIF_FRAC 140
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#define CLK_SPDIF 141
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#define MCLK_SPDIF 142
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#define HCLK_SDMMC0 143
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#define CCLK_SDMMC0 144
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#define HCLK_SDMMC1 145
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#define CCLK_SDMMC1 146
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#define SCLK_SDMMC0_DRV 147
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#define SCLK_SDMMC0_SAMPLE 148
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#define SCLK_SDMMC1_DRV 149
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#define SCLK_SDMMC1_SAMPLE 150
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#define HCLK_EMMC 151
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#define ACLK_EMMC 152
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#define CCLK_EMMC 153
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#define BCLK_EMMC 154
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#define TMCLK_EMMC 155
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#define SCLK_SFC 156
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#define HCLK_SFC 157
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#define HCLK_USB2HOST 158
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#define HCLK_USB2HOST_ARB 159
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#define PCLK_SPI1 160
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#define CLK_SPI1 161
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#define SCLK_IN_SPI1 162
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#define PCLK_SPI2 163
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#define CLK_SPI2 164
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#define SCLK_IN_SPI2 165
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#define PCLK_UART1 166
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#define PCLK_UART2 167
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#define PCLK_UART3 168
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#define PCLK_UART4 169
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#define PCLK_UART5 170
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#define PCLK_UART6 171
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#define PCLK_UART7 172
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#define PCLK_UART8 173
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#define PCLK_UART9 174
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#define CLK_UART1_SRC 175
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#define CLK_UART1_FRAC 176
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#define CLK_UART1 177
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#define SCLK_UART1 178
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#define CLK_UART2_SRC 179
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#define CLK_UART2_FRAC 180
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#define CLK_UART2 181
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#define SCLK_UART2 182
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#define CLK_UART3_SRC 183
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#define CLK_UART3_FRAC 184
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#define CLK_UART3 185
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#define SCLK_UART3 186
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#define CLK_UART4_SRC 187
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#define CLK_UART4_FRAC 188
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#define CLK_UART4 189
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#define SCLK_UART4 190
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#define CLK_UART5_SRC 191
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#define CLK_UART5_FRAC 192
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#define CLK_UART5 193
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#define SCLK_UART5 194
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#define CLK_UART6_SRC 195
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#define CLK_UART6_FRAC 196
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#define CLK_UART6 197
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#define SCLK_UART6 198
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#define CLK_UART7_SRC 199
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#define CLK_UART7_FRAC 200
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#define CLK_UART7 201
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#define SCLK_UART7 202
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#define CLK_UART8_SRC 203
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#define CLK_UART8_FRAC 204
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#define CLK_UART8 205
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#define SCLK_UART8 206
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#define CLK_UART9_SRC 207
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#define CLK_UART9_FRAC 208
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#define CLK_UART9 209
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#define SCLK_UART9 210
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#define PCLK_PWM1_PERI 211
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#define CLK_PWM1_PERI 212
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#define CLK_CAPTURE_PWM1_PERI 213
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#define PCLK_PWM2_PERI 214
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#define CLK_PWM2_PERI 215
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#define CLK_CAPTURE_PWM2_PERI 216
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#define PCLK_PWM3_PERI 217
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#define CLK_PWM3_PERI 218
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#define CLK_CAPTURE_PWM3_PERI 219
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#define PCLK_CAN0 220
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#define CLK_CAN0 221
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#define PCLK_CAN1 222
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#define CLK_CAN1 223
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#define ACLK_CRYPTO 224
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#define HCLK_CRYPTO 225
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#define PCLK_CRYPTO 226
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#define CLK_CORE_CRYPTO 227
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#define CLK_PKA_CRYPTO 228
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#define HCLK_KLAD 229
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#define PCLK_KEY_READER 230
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#define HCLK_RK_RNG_NS 231
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#define HCLK_RK_RNG_S 232
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#define HCLK_TRNG_NS 233
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#define HCLK_TRNG_S 234
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#define HCLK_CRYPTO_S 235
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#define PCLK_PERI_WDT 236
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#define TCLK_PERI_WDT 237
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#define ACLK_SYSMEM 238
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#define HCLK_BOOTROM 239
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#define PCLK_PERI_GRF 240
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#define ACLK_DMAC 241
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#define ACLK_RKDMAC 242
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#define PCLK_OTPC_NS 243
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#define CLK_SBPI_OTPC_NS 244
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#define CLK_USER_OTPC_NS 245
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#define PCLK_OTPC_S 246
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#define CLK_SBPI_OTPC_S 247
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#define CLK_USER_OTPC_S 248
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#define CLK_OTPC_ARB 249
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#define PCLK_OTPPHY 250
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#define PCLK_USB2PHY 251
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#define PCLK_PIPEPHY 252
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#define PCLK_SARADC 253
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#define CLK_SARADC 254
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#define PCLK_IOC_VCCIO234 255
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#define PCLK_PERI_GPIO1 256
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#define PCLK_PERI_GPIO2 257
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#define DCLK_PERI_GPIO 258
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#define DCLK_PERI_GPIO1 259
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#define DCLK_PERI_GPIO2 260
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#define ACLK_PHP 261
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#define PCLK_PHP 262
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#define ACLK_PCIE20_MST 263
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#define ACLK_PCIE20_SLV 264
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#define ACLK_PCIE20_DBI 265
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#define PCLK_PCIE20 266
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#define CLK_PCIE20_AUX 267
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#define ACLK_USB3OTG 268
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#define CLK_USB3OTG_SUSPEND 269
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#define CLK_USB3OTG_REF 270
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#define CLK_PIPEPHY_REF_FUNC 271
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#define CLK_200M_PMU 272
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#define CLK_RTC_32K 273
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#define CLK_RTC32K_FRAC 274
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#define BUSCLK_PDPMU0 275
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#define PCLK_PMU0_CRU 276
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#define PCLK_PMU0_PMU 277
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#define CLK_PMU0_PMU 278
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#define PCLK_PMU0_HP_TIMER 279
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#define CLK_PMU0_HP_TIMER 280
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#define CLK_PMU0_32K_HP_TIMER 281
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#define PCLK_PMU0_PVTM 282
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#define CLK_PMU0_PVTM 283
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#define PCLK_IOC_PMUIO 284
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#define PCLK_PMU0_GPIO0 285
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#define DBCLK_PMU0_GPIO0 286
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#define PCLK_PMU0_GRF 287
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#define PCLK_PMU0_SGRF 288
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#define CLK_DDR_FAIL_SAFE 289
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#define PCLK_PMU0_SCRKEYGEN 290
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#define PCLK_PMU1_CRU 291
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#define HCLK_PMU1_MEM 292
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#define PCLK_PMU0_I2C0 293
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#define CLK_PMU0_I2C0 294
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#define PCLK_PMU1_UART0 295
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#define CLK_PMU1_UART0_SRC 296
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#define CLK_PMU1_UART0_FRAC 297
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#define CLK_PMU1_UART0 298
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#define SCLK_PMU1_UART0 299
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#define PCLK_PMU1_SPI0 300
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#define CLK_PMU1_SPI0 301
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#define SCLK_IN_PMU1_SPI0 302
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#define PCLK_PMU1_PWM0 303
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#define CLK_PMU1_PWM0 304
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#define CLK_CAPTURE_PMU1_PWM0 305
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#define CLK_PMU1_WIFI 306
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#define FCLK_PMU1_CM0_CORE 307
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#define CLK_PMU1_CM0_RTC 308
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#define PCLK_PMU1_WDTNS 309
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#define CLK_PMU1_WDTNS 310
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#define PCLK_PMU1_MAILBOX 311
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#define CLK_PIPEPHY_DIV 312
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#define CLK_PIPEPHY_XIN24M 313
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#define CLK_PIPEPHY_REF 314
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#define CLK_24M_SSCSRC 315
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#define CLK_USB2PHY_XIN24M 316
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#define CLK_USB2PHY_REF 317
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#define CLK_MIPIDSIPHY_XIN24M 318
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#define CLK_MIPIDSIPHY_REF 319
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#define ACLK_RGA_PRE 320
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#define HCLK_RGA_PRE 321
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#define ACLK_RGA 322
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#define HCLK_RGA 323
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#define CLK_RGA_CORE 324
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#define ACLK_JDEC 325
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#define HCLK_JDEC 326
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#define ACLK_VDPU_PRE 327
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#define CLK_RKVDEC_HEVC_CA 328
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#define HCLK_VDPU_PRE 329
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#define ACLK_RKVDEC 330
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#define HCLK_RKVDEC 331
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#define CLK_RKVENC_CORE 332
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#define ACLK_VEPU_PRE 333
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#define HCLK_VEPU_PRE 334
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#define ACLK_RKVENC 335
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#define HCLK_RKVENC 336
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#define ACLK_VI 337
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#define HCLK_VI 338
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#define PCLK_VI 339
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#define ACLK_ISP 340
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#define HCLK_ISP 341
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#define CLK_ISP 342
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#define ACLK_VICAP 343
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#define HCLK_VICAP 344
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#define DCLK_VICAP 345
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#define CSIRX0_CLK_DATA 346
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#define CSIRX1_CLK_DATA 347
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#define CSIRX2_CLK_DATA 348
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#define CSIRX3_CLK_DATA 349
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#define PCLK_CSIHOST0 350
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#define PCLK_CSIHOST1 351
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#define PCLK_CSIHOST2 352
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#define PCLK_CSIHOST3 353
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#define PCLK_CSIPHY0 354
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#define PCLK_CSIPHY1 355
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#define ACLK_VO_PRE 356
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#define HCLK_VO_PRE 357
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#define ACLK_VOP 358
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#define HCLK_VOP 359
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#define DCLK_VOP 360
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#define DCLK_VOP1 361
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#define ACLK_CRYPTO_S 362
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#define PCLK_CRYPTO_S 363
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#define CLK_CORE_CRYPTO_S 364
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#define CLK_PKA_CRYPTO_S 365
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#endif
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