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8b1750ea00
Add DT bindings for the Display clock on QCS615 platforms. Add the relevant DT include definitions as well. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-4-9c216e1615ab@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
53 lines
1.7 KiB
C
53 lines
1.7 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_QCS615_H
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#define _DT_BINDINGS_CLK_QCOM_DISP_CC_QCS615_H
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/* DISP_CC clocks */
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#define DISP_CC_MDSS_AHB_CLK 0
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#define DISP_CC_MDSS_AHB_CLK_SRC 1
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#define DISP_CC_MDSS_BYTE0_CLK 2
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#define DISP_CC_MDSS_BYTE0_CLK_SRC 3
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#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 4
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#define DISP_CC_MDSS_BYTE0_INTF_CLK 5
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#define DISP_CC_MDSS_DP_AUX_CLK 6
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#define DISP_CC_MDSS_DP_AUX_CLK_SRC 7
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#define DISP_CC_MDSS_DP_CRYPTO_CLK 8
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#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 9
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#define DISP_CC_MDSS_DP_LINK_CLK 10
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#define DISP_CC_MDSS_DP_LINK_CLK_SRC 11
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#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 12
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#define DISP_CC_MDSS_DP_LINK_INTF_CLK 13
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#define DISP_CC_MDSS_DP_PIXEL1_CLK 14
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#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 15
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#define DISP_CC_MDSS_DP_PIXEL_CLK 16
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#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 17
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#define DISP_CC_MDSS_ESC0_CLK 18
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#define DISP_CC_MDSS_ESC0_CLK_SRC 19
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#define DISP_CC_MDSS_MDP_CLK 20
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#define DISP_CC_MDSS_MDP_CLK_SRC 21
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#define DISP_CC_MDSS_MDP_LUT_CLK 22
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#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 23
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#define DISP_CC_MDSS_PCLK0_CLK 24
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#define DISP_CC_MDSS_PCLK0_CLK_SRC 25
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#define DISP_CC_MDSS_ROT_CLK 26
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#define DISP_CC_MDSS_ROT_CLK_SRC 27
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#define DISP_CC_MDSS_RSCC_AHB_CLK 28
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#define DISP_CC_MDSS_RSCC_VSYNC_CLK 29
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#define DISP_CC_MDSS_VSYNC_CLK 30
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#define DISP_CC_MDSS_VSYNC_CLK_SRC 31
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#define DISP_CC_PLL0 32
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#define DISP_CC_XO_CLK 33
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/* DISP_CC power domains */
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#define MDSS_CORE_GDSC 0
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/* DISP_CC resets */
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#define DISP_CC_MDSS_CORE_BCR 0
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#define DISP_CC_MDSS_RSCC_BCR 1
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#endif
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