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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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d3cbe455d6
RK3576 SoC contains a UFS controller, add initial support for it. The features are: 1. support UFS 2.0 features 2. High speed up to HS-G3 3. 2RX-2TX lanes 4. auto H8 entry and exit Software limitation: 1. HCE procedure: enable controller->enable intr->dme_reset->dme_enable 2. disable unipro timeout values before power mode change [mkp: fix build errors] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Link: https://lore.kernel.org/r/1738736156-119203-7-git-send-email-shawn.lin@rock-chips.com Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
91 lines
3.2 KiB
C
91 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Rockchip UFS Host Controller driver
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*
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* Copyright (C) 2025 Rockchip Electronics Co., Ltd.
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*/
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#ifndef _UFS_ROCKCHIP_H_
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#define _UFS_ROCKCHIP_H_
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#define SEL_TX_LANE0 0x0
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#define SEL_TX_LANE1 0x1
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#define SEL_TX_LANE2 0x2
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#define SEL_TX_LANE3 0x3
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#define SEL_RX_LANE0 0x4
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#define SEL_RX_LANE1 0x5
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#define SEL_RX_LANE2 0x6
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#define SEL_RX_LANE3 0x7
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#define VND_TX_CLK_PRD 0xAA
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#define VND_TX_CLK_PRD_EN 0xA9
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#define VND_TX_LINERESET_PVALUE2 0xAB
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#define VND_TX_LINERESET_PVALUE1 0xAC
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#define VND_TX_LINERESET_VALUE 0xAD
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#define VND_TX_BASE_NVALUE 0x93
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#define VND_TX_TASE_VALUE 0x94
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#define VND_TX_POWER_SAVING_CTRL 0x7F
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#define VND_RX_CLK_PRD 0x12
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#define VND_RX_CLK_PRD_EN 0x11
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#define VND_RX_LINERESET_PVALUE2 0x1B
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#define VND_RX_LINERESET_PVALUE1 0x1C
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#define VND_RX_LINERESET_VALUE 0x1D
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#define VND_RX_LINERESET_OPTION 0x25
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#define VND_RX_POWER_SAVING_CTRL 0x2F
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#define VND_RX_SAVE_DET_CTRL 0x1E
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#define CMN_REG23 0x8C
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#define CMN_REG25 0x94
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#define TRSV0_REG08 0xE0
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#define TRSV1_REG08 0x220
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#define TRSV0_REG14 0x110
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#define TRSV1_REG14 0x250
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#define TRSV0_REG15 0x134
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#define TRSV1_REG15 0x274
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#define TRSV0_REG16 0x128
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#define TRSV1_REG16 0x268
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#define TRSV0_REG17 0x12C
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#define TRSV1_REG17 0x26c
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#define TRSV0_REG18 0x120
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#define TRSV1_REG18 0x260
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#define TRSV0_REG29 0x164
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#define TRSV1_REG29 0x2A4
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#define TRSV0_REG2E 0x178
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#define TRSV1_REG2E 0x2B8
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#define TRSV0_REG3C 0x1B0
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#define TRSV1_REG3C 0x2F0
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#define TRSV0_REG3D 0x1B4
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#define TRSV1_REG3D 0x2F4
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#define MPHY_CFG 0x200
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#define MPHY_CFG_ENABLE 0x40
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#define MPHY_CFG_DISABLE 0x0
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#define MIB_T_DBG_CPORT_TX_ENDIAN 0xc022
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#define MIB_T_DBG_CPORT_RX_ENDIAN 0xc023
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struct ufs_rockchip_host {
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struct ufs_hba *hba;
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void __iomem *ufs_phy_ctrl;
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void __iomem *ufs_sys_ctrl;
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void __iomem *mphy_base;
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struct gpio_desc *rst_gpio;
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struct reset_control *rst;
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struct clk *ref_out_clk;
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struct clk_bulk_data *clks;
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uint64_t caps;
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};
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#define ufs_sys_writel(base, val, reg) \
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writel((val), (base) + (reg))
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#define ufs_sys_readl(base, reg) readl((base) + (reg))
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#define ufs_sys_set_bits(base, mask, reg) \
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ufs_sys_writel( \
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(base), ((mask) | (ufs_sys_readl((base), (reg)))), (reg))
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#define ufs_sys_ctrl_clr_bits(base, mask, reg) \
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ufs_sys_writel((base), \
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((~(mask)) & (ufs_sys_readl((base), (reg)))), \
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(reg))
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#endif /* _UFS_ROCKCHIP_H_ */
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