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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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3903b4701b
Add SoC identification for the RZ/V2N SoC using the System Controller (SYS) block. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250415085438.83856-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
76 lines
2.2 KiB
C
76 lines
2.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* RZ/V2N System controller (SYS) driver
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*
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* Copyright (C) 2025 Renesas Electronics Corp.
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*/
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include "rz-sysc.h"
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/* Register Offsets */
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#define SYS_LSI_MODE 0x300
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#define SYS_LSI_MODE_SEC_EN BIT(16)
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/*
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* BOOTPLLCA[1:0]
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* [0,0] => 1.1GHZ
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* [0,1] => 1.5GHZ
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* [1,0] => 1.6GHZ
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* [1,1] => 1.7GHZ
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*/
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#define SYS_LSI_MODE_STAT_BOOTPLLCA55 GENMASK(12, 11)
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#define SYS_LSI_MODE_CA55_1_7GHZ 0x3
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#define SYS_LSI_PRR 0x308
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#define SYS_LSI_PRR_GPU_DIS BIT(0)
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#define SYS_LSI_PRR_ISP_DIS BIT(4)
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#define SYS_RZV2N_FEATURE_G31 BIT(0)
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#define SYS_RZV2N_FEATURE_C55 BIT(1)
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#define SYS_RZV2N_FEATURE_SEC BIT(2)
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static void rzv2n_sys_print_id(struct device *dev,
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void __iomem *sysc_base,
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struct soc_device_attribute *soc_dev_attr)
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{
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u32 prr_val, mode_val;
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u8 feature_flags;
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prr_val = readl(sysc_base + SYS_LSI_PRR);
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mode_val = readl(sysc_base + SYS_LSI_MODE);
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/* Check GPU, ISP and Cryptographic configuration */
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feature_flags = !(prr_val & SYS_LSI_PRR_GPU_DIS) ? SYS_RZV2N_FEATURE_G31 : 0;
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feature_flags |= !(prr_val & SYS_LSI_PRR_ISP_DIS) ? SYS_RZV2N_FEATURE_C55 : 0;
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feature_flags |= (mode_val & SYS_LSI_MODE_SEC_EN) ? SYS_RZV2N_FEATURE_SEC : 0;
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dev_info(dev, "Detected Renesas %s %sn%d Rev %s%s%s%s%s\n", soc_dev_attr->family,
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soc_dev_attr->soc_id, 41 + feature_flags, soc_dev_attr->revision,
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feature_flags ? " with" : "",
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feature_flags & SYS_RZV2N_FEATURE_G31 ? " GE3D (Mali-G31)" : "",
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feature_flags & SYS_RZV2N_FEATURE_SEC ? " Cryptographic engine" : "",
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feature_flags & SYS_RZV2N_FEATURE_C55 ? " ISP (Mali-C55)" : "");
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/* Check CA55 PLL configuration */
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if (FIELD_GET(SYS_LSI_MODE_STAT_BOOTPLLCA55, mode_val) != SYS_LSI_MODE_CA55_1_7GHZ)
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dev_warn(dev, "CA55 PLL is not set to 1.7GHz\n");
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}
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static const struct rz_sysc_soc_id_init_data rzv2n_sys_soc_id_init_data __initconst = {
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.family = "RZ/V2N",
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.id = 0x867d447,
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.devid_offset = 0x304,
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.revision_mask = GENMASK(31, 28),
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.specific_id_mask = GENMASK(27, 0),
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.print_id = rzv2n_sys_print_id,
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};
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const struct rz_sysc_init_data rzv2n_sys_init_data = {
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.soc_id_init_data = &rzv2n_sys_soc_id_init_data,
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};
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