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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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d07470cff5
Add SoC detection support for the RZ/G3E SoC. Also add support for detecting the number of cores and the ETHOS-U55 NPU, and also detect PLL mismatch for SW settings other than 1.7GHz. Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250128031342.52675-4-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
68 lines
1.8 KiB
C
68 lines
1.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* RZ/G3E System controller (SYS) driver
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*
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* Copyright (C) 2025 Renesas Electronics Corp.
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*/
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include "rz-sysc.h"
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/* Register Offsets */
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#define SYS_LSI_MODE 0x300
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/*
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* BOOTPLLCA[1:0]
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* [0,0] => 1.1GHZ
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* [0,1] => 1.5GHZ
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* [1,0] => 1.6GHZ
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* [1,1] => 1.7GHZ
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*/
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#define SYS_LSI_MODE_STAT_BOOTPLLCA55 GENMASK(12, 11)
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#define SYS_LSI_MODE_CA55_1_7GHZ 0x3
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#define SYS_LSI_PRR 0x308
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#define SYS_LSI_PRR_CA55_DIS BIT(8)
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#define SYS_LSI_PRR_NPU_DIS BIT(1)
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static void rzg3e_sys_print_id(struct device *dev,
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void __iomem *sysc_base,
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struct soc_device_attribute *soc_dev_attr)
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{
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bool is_quad_core, npu_enabled;
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u32 prr_val, mode_val;
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prr_val = readl(sysc_base + SYS_LSI_PRR);
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mode_val = readl(sysc_base + SYS_LSI_MODE);
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/* Check CPU and NPU configuration */
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is_quad_core = !(prr_val & SYS_LSI_PRR_CA55_DIS);
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npu_enabled = !(prr_val & SYS_LSI_PRR_NPU_DIS);
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dev_info(dev, "Detected Renesas %s Core %s %s Rev %s%s\n",
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is_quad_core ? "Quad" : "Dual", soc_dev_attr->family,
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soc_dev_attr->soc_id, soc_dev_attr->revision,
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npu_enabled ? " with Ethos-U55" : "");
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/* Check CA55 PLL configuration */
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if (FIELD_GET(SYS_LSI_MODE_STAT_BOOTPLLCA55, mode_val) != SYS_LSI_MODE_CA55_1_7GHZ)
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dev_warn(dev, "CA55 PLL is not set to 1.7GHz\n");
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}
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static const struct rz_sysc_soc_id_init_data rzg3e_sys_soc_id_init_data __initconst = {
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.family = "RZ/G3E",
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.id = 0x8679447,
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.devid_offset = 0x304,
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.revision_mask = GENMASK(31, 28),
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.specific_id_mask = GENMASK(27, 0),
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.print_id = rzg3e_sys_print_id,
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};
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const struct rz_sysc_init_data rzg3e_sys_init_data = {
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.soc_id_init_data = &rzg3e_sys_soc_id_init_data,
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};
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