mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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aa0f05dcf3
Now that all of the mmsys routing tables have been fixed, migrate all of them to use the MMSYS_ROUTE() macro: this will make sure that future additions to any of the tables for the currently supported SoCs are compile-time sanity checked, greatly reducing room for (way too common) mistakes. Link: https://lore.kernel.org/r/20250212100012.33001-8-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
67 lines
2.5 KiB
C
67 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __SOC_MEDIATEK_MT8192_MMSYS_H
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#define __SOC_MEDIATEK_MT8192_MMSYS_H
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#define MT8192_MMSYS_OVL_MOUT_EN 0xf04
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#define MT8192_DISP_OVL1_2L_MOUT_EN 0xf08
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#define MT8192_DISP_OVL0_2L_MOUT_EN 0xf18
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#define MT8192_DISP_OVL0_MOUT_EN 0xf1c
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#define MT8192_DISP_RDMA0_SEL_IN 0xf2c
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#define MT8192_DISP_RDMA0_SOUT_SEL 0xf30
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#define MT8192_DISP_CCORR0_SOUT_SEL 0xf34
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#define MT8192_DISP_AAL0_SEL_IN 0xf38
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#define MT8192_DISP_DITHER0_MOUT_EN 0xf3c
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#define MT8192_DISP_DSI0_SEL_IN 0xf40
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#define MT8192_DISP_OVL2_2L_MOUT_EN 0xf4c
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#define MT8192_DISP_OVL0_GO_BLEND BIT(0)
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#define MT8192_DITHER0_MOUT_IN_DSI0 BIT(0)
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#define MT8192_OVL0_MOUT_EN_DISP_RDMA0 BIT(0)
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#define MT8192_OVL2_2L_MOUT_EN_RDMA4 BIT(0)
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#define MT8192_DISP_OVL0_GO_BG BIT(1)
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#define MT8192_DISP_OVL0_2L_GO_BLEND BIT(2)
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#define MT8192_DISP_OVL0_2L_GO_BG BIT(3)
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#define MT8192_OVL1_2L_MOUT_EN_RDMA1 BIT(4)
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#define MT8192_OVL0_MOUT_EN_OVL0_2L BIT(4)
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#define MT8192_RDMA0_SEL_IN_OVL0_2L 0x3
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#define MT8192_RDMA0_SOUT_COLOR0 0x1
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#define MT8192_CCORR0_SOUT_AAL0 0x1
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#define MT8192_AAL0_SEL_IN_CCORR0 0x1
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#define MT8192_DSI0_SEL_IN_DITHER0 0x1
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static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
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MMSYS_ROUTE(OVL_2L0, RDMA0,
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MT8192_DISP_OVL0_2L_MOUT_EN, MT8192_OVL0_MOUT_EN_DISP_RDMA0,
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MT8192_OVL0_MOUT_EN_DISP_RDMA0),
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MMSYS_ROUTE(OVL_2L2, RDMA4,
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MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4,
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MT8192_OVL2_2L_MOUT_EN_RDMA4),
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MMSYS_ROUTE(DITHER0, DSI0,
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MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0,
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MT8192_DITHER0_MOUT_IN_DSI0),
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MMSYS_ROUTE(OVL_2L0, RDMA0,
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MT8192_DISP_RDMA0_SEL_IN, MT8192_RDMA0_SEL_IN_OVL0_2L,
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MT8192_RDMA0_SEL_IN_OVL0_2L),
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MMSYS_ROUTE(CCORR, AAL0,
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MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0,
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MT8192_AAL0_SEL_IN_CCORR0),
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MMSYS_ROUTE(DITHER0, DSI0,
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MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0,
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MT8192_DSI0_SEL_IN_DITHER0),
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MMSYS_ROUTE(RDMA0, COLOR0,
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MT8192_DISP_RDMA0_SOUT_SEL, MT8192_RDMA0_SOUT_COLOR0,
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MT8192_RDMA0_SOUT_COLOR0),
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MMSYS_ROUTE(CCORR, AAL0,
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MT8192_DISP_CCORR0_SOUT_SEL, MT8192_CCORR0_SOUT_AAL0,
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MT8192_CCORR0_SOUT_AAL0),
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MMSYS_ROUTE(OVL0, OVL_2L0,
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MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_GO_BG,
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MT8192_DISP_OVL0_GO_BG),
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MMSYS_ROUTE(OVL_2L0, RDMA0,
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MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_2L_GO_BLEND,
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MT8192_DISP_OVL0_2L_GO_BLEND),
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};
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#endif /* __SOC_MEDIATEK_MT8192_MMSYS_H */
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