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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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aa0f05dcf3
Now that all of the mmsys routing tables have been fixed, migrate all of them to use the MMSYS_ROUTE() macro: this will make sure that future additions to any of the tables for the currently supported SoCs are compile-time sanity checked, greatly reducing room for (way too common) mistakes. Link: https://lore.kernel.org/r/20250212100012.33001-8-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
56 lines
2.0 KiB
C
56 lines
2.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __SOC_MEDIATEK_MT8183_MMSYS_H
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#define __SOC_MEDIATEK_MT8183_MMSYS_H
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#define MT8183_DISP_OVL0_MOUT_EN 0xf00
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#define MT8183_DISP_OVL0_2L_MOUT_EN 0xf04
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#define MT8183_DISP_OVL1_2L_MOUT_EN 0xf08
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#define MT8183_DISP_DITHER0_MOUT_EN 0xf0c
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#define MT8183_DISP_PATH0_SEL_IN 0xf24
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#define MT8183_DISP_DSI0_SEL_IN 0xf2c
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#define MT8183_DISP_DPI0_SEL_IN 0xf30
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#define MT8183_DISP_RDMA0_SOUT_SEL_IN 0xf50
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#define MT8183_DISP_RDMA1_SOUT_SEL_IN 0xf54
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#define MT8183_OVL0_MOUT_EN_OVL0_2L BIT(4)
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#define MT8183_OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0)
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#define MT8183_OVL1_2L_MOUT_EN_RDMA1 BIT(4)
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#define MT8183_DITHER0_MOUT_IN_DSI0 BIT(0)
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#define MT8183_DISP_PATH0_SEL_IN_OVL0_2L 0x1
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#define MT8183_DSI0_SEL_IN_RDMA0 0x1
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#define MT8183_DSI0_SEL_IN_RDMA1 0x3
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#define MT8183_DPI0_SEL_IN_RDMA0 0x1
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#define MT8183_DPI0_SEL_IN_RDMA1 0x2
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#define MT8183_RDMA0_SOUT_COLOR0 0x1
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#define MT8183_RDMA1_SOUT_DSI0 0x1
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#define MT8183_MMSYS_SW0_RST_B 0x140
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static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
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MMSYS_ROUTE(OVL0, OVL_2L0,
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MT8183_DISP_OVL0_MOUT_EN, MT8183_OVL0_MOUT_EN_OVL0_2L,
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MT8183_OVL0_MOUT_EN_OVL0_2L),
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MMSYS_ROUTE(OVL_2L0, RDMA0,
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MT8183_DISP_OVL0_2L_MOUT_EN, MT8183_OVL0_2L_MOUT_EN_DISP_PATH0,
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MT8183_OVL0_2L_MOUT_EN_DISP_PATH0),
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MMSYS_ROUTE(OVL_2L1, RDMA1,
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MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1,
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MT8183_OVL1_2L_MOUT_EN_RDMA1),
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MMSYS_ROUTE(DITHER0, DSI0,
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MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0,
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MT8183_DITHER0_MOUT_IN_DSI0),
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MMSYS_ROUTE(OVL_2L0, RDMA0,
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MT8183_DISP_PATH0_SEL_IN, MT8183_DISP_PATH0_SEL_IN_OVL0_2L,
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MT8183_DISP_PATH0_SEL_IN_OVL0_2L),
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MMSYS_ROUTE(RDMA1, DPI0,
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MT8183_DISP_DPI0_SEL_IN, MT8183_DPI0_SEL_IN_RDMA1,
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MT8183_DPI0_SEL_IN_RDMA1),
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MMSYS_ROUTE(RDMA0, COLOR0,
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MT8183_DISP_RDMA0_SOUT_SEL_IN, MT8183_RDMA0_SOUT_COLOR0,
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MT8183_RDMA0_SOUT_COLOR0),
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};
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#endif /* __SOC_MEDIATEK_MT8183_MMSYS_H */
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