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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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aa0f05dcf3
Now that all of the mmsys routing tables have been fixed, migrate all of them to use the MMSYS_ROUTE() macro: this will make sure that future additions to any of the tables for the currently supported SoCs are compile-time sanity checked, greatly reducing room for (way too common) mistakes. Link: https://lore.kernel.org/r/20250212100012.33001-8-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
81 lines
3.3 KiB
C
81 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __SOC_MEDIATEK_MT8173_MMSYS_H
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#define __SOC_MEDIATEK_MT8173_MMSYS_H
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#define MT8173_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
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#define MT8173_DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
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#define MT8173_DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
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#define MT8173_DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
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#define MT8173_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
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#define MT8173_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
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#define MT8173_DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
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#define MT8173_DISP_REG_CONFIG_DISP_AAL_SEL_IN 0x08c
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#define MT8173_DISP_REG_CONFIG_DISP_UFOE_SEL_IN 0x0a0
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#define MT8173_DISP_REG_CONFIG_DSI0_SEL_IN 0x0a4
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#define MT8173_DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
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#define MT8173_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN 0x0b0
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#define MT8173_DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
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#define MT8173_DISP_REG_CONFIG_DISP_COLOR0_SOUT_SEL_IN 0x0bc
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#define MT8173_AAL_SEL_IN_MERGE BIT(0)
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#define MT8173_COLOR0_SEL_IN_OVL0 BIT(0)
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#define MT8173_COLOR0_SOUT_MERGE BIT(0)
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#define MT8173_DPI0_SEL_IN_MASK GENMASK(1, 0)
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#define MT8173_DPI0_SEL_IN_RDMA1 BIT(0)
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#define MT8173_DSI0_SEL_IN_UFOE BIT(0)
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#define MT8173_GAMMA_MOUT_EN_RDMA1 BIT(0)
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#define MT8173_OD0_MOUT_EN_RDMA0 BIT(0)
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#define MT8173_OVL0_MOUT_EN_COLOR0 BIT(0)
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#define MT8173_OVL1_MOUT_EN_COLOR1 BIT(0)
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#define MT8173_UFOE_MOUT_EN_DSI0 BIT(0)
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#define MT8173_UFOE_SEL_IN_RDMA0 BIT(0)
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#define MT8173_RDMA0_SOUT_COLOR0 BIT(0)
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static const struct mtk_mmsys_routes mt8173_mmsys_routing_table[] = {
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MMSYS_ROUTE(OVL0, COLOR0,
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MT8173_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, MT8173_OVL0_MOUT_EN_COLOR0,
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MT8173_OVL0_MOUT_EN_COLOR0),
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MMSYS_ROUTE(OD0, RDMA0,
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MT8173_DISP_REG_CONFIG_DISP_OD_MOUT_EN, MT8173_OD0_MOUT_EN_RDMA0,
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MT8173_OD0_MOUT_EN_RDMA0),
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MMSYS_ROUTE(UFOE, DSI0,
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MT8173_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, MT8173_UFOE_MOUT_EN_DSI0,
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MT8173_UFOE_MOUT_EN_DSI0),
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MMSYS_ROUTE(COLOR0, AAL0,
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MT8173_DISP_REG_CONFIG_DISP_COLOR0_SOUT_SEL_IN, MT8173_COLOR0_SOUT_MERGE,
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0 /* SOUT to AAL */),
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MMSYS_ROUTE(RDMA0, UFOE,
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MT8173_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8173_RDMA0_SOUT_COLOR0,
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0 /* SOUT to UFOE */),
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MMSYS_ROUTE(OVL0, COLOR0,
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MT8173_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, MT8173_COLOR0_SEL_IN_OVL0,
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MT8173_COLOR0_SEL_IN_OVL0),
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MMSYS_ROUTE(AAL0, COLOR0,
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MT8173_DISP_REG_CONFIG_DISP_AAL_SEL_IN, MT8173_AAL_SEL_IN_MERGE,
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0 /* SEL_IN from COLOR0 */),
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MMSYS_ROUTE(RDMA0, UFOE,
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MT8173_DISP_REG_CONFIG_DISP_UFOE_SEL_IN, MT8173_UFOE_SEL_IN_RDMA0,
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0 /* SEL_IN from RDMA0 */),
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MMSYS_ROUTE(UFOE, DSI0,
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MT8173_DISP_REG_CONFIG_DSI0_SEL_IN, MT8173_DSI0_SEL_IN_UFOE,
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0 /* SEL_IN from UFOE */),
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MMSYS_ROUTE(OVL1, COLOR1,
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MT8173_DISP_REG_CONFIG_DISP_OVL1_MOUT_EN, MT8173_OVL1_MOUT_EN_COLOR1,
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MT8173_OVL1_MOUT_EN_COLOR1),
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MMSYS_ROUTE(GAMMA, RDMA1,
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MT8173_DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN, MT8173_GAMMA_MOUT_EN_RDMA1,
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MT8173_GAMMA_MOUT_EN_RDMA1),
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MMSYS_ROUTE(RDMA1, DPI0,
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MT8173_DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
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RDMA1_SOUT_DPI0),
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MMSYS_ROUTE(OVL1, COLOR1,
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MT8173_DISP_REG_CONFIG_DISP_COLOR1_SEL_IN, COLOR1_SEL_IN_OVL1,
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COLOR1_SEL_IN_OVL1),
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MMSYS_ROUTE(RDMA1, DPI0,
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MT8173_DISP_REG_CONFIG_DPI_SEL_IN, MT8173_DPI0_SEL_IN_MASK,
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MT8173_DPI0_SEL_IN_RDMA1),
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};
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#endif /* __SOC_MEDIATEK_MT8173_MMSYS_H */
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