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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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b8a51e95b3
As most other Allwinner SoCs before, the A523 chip contains a second GPIO controller, managing banks PL and PM. Use the newly introduced DT based pinctrl driver to describe just the generic pinctrl properties, so advertise the number of pins per bank and the interrupt capabilities. The actual function/mux assignment is taken from the devicetree. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/20250306235827.4895-9-andre.przywara@arm.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
55 lines
1.3 KiB
C
55 lines
1.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Allwinner A523 SoC r-pinctrl driver.
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*
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* Copyright (C) 2024 Arm Ltd.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/pinctrl.h>
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#include "pinctrl-sunxi.h"
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static const u8 a523_r_nr_bank_pins[SUNXI_PINCTRL_MAX_BANKS] =
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/* PL PM */
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{ 14, 6 };
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static const unsigned int a523_r_irq_bank_map[] = { 0, 1 };
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static const u8 a523_r_irq_bank_muxes[SUNXI_PINCTRL_MAX_BANKS] =
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/* PL PM */
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{ 14, 14 };
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static struct sunxi_pinctrl_desc a523_r_pinctrl_data = {
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.irq_banks = ARRAY_SIZE(a523_r_irq_bank_map),
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.irq_bank_map = a523_r_irq_bank_map,
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.irq_read_needs_mux = true,
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.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
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.pin_base = PL_BASE,
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};
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static int a523_r_pinctrl_probe(struct platform_device *pdev)
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{
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return sunxi_pinctrl_dt_table_init(pdev, a523_r_nr_bank_pins,
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a523_r_irq_bank_muxes,
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&a523_r_pinctrl_data,
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SUNXI_PINCTRL_NEW_REG_LAYOUT);
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}
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static const struct of_device_id a523_r_pinctrl_match[] = {
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{ .compatible = "allwinner,sun55i-a523-r-pinctrl", },
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{}
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};
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static struct platform_driver a523_r_pinctrl_driver = {
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.probe = a523_r_pinctrl_probe,
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.driver = {
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.name = "sun55i-a523-r-pinctrl",
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.of_match_table = a523_r_pinctrl_match,
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},
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};
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builtin_platform_driver(a523_r_pinctrl_driver);
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