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a30692b4f8
Newer Exynos based SoCs have a filter selection bitfield in the filter configuration registers on alive bank pins. This allows the selection of a digital or analog delay filter for each pin. Add support for selecting and enabling the filter. On suspend we set the analog filter to all pins in the bank (as the digital filter relies on a clock). On resume the digital filter is reapplied to all pins in the bank. The digital filter is working via a clock and has an adjustable filter delay flt_width bitfield, whereas the analog filter uses a fixed delay. The filter determines to what extent signal fluctuations received through the pad are considered glitches. The code path can be exercised using echo mem > /sys/power/state And then wake the device using a eint gpio Reviewed-by: André Draszik <andre.draszik@linaro.org> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20250402-pinctrl-fltcon-suspend-v6-4-78ce0d4eb30c@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
274 lines
7.7 KiB
C
274 lines
7.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Exynos specific definitions for Samsung pinctrl and gpiolib driver.
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*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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* Copyright (c) 2012 Linaro Ltd
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* http://www.linaro.org
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*
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* This file contains the Exynos specific definitions for the Samsung
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* pinctrl/gpiolib interface drivers.
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*
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* Author: Thomas Abraham <thomas.ab@samsung.com>
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*/
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#ifndef __PINCTRL_SAMSUNG_EXYNOS_H
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#define __PINCTRL_SAMSUNG_EXYNOS_H
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/* Values for the pin CON register */
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#define EXYNOS_PIN_CON_FUNC_EINT 0xf
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/* External GPIO and wakeup interrupt related definitions */
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#define EXYNOS_GPIO_ECON_OFFSET 0x700
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#define EXYNOS_GPIO_EFLTCON_OFFSET 0x800
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#define EXYNOS_GPIO_EMASK_OFFSET 0x900
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#define EXYNOS_GPIO_EPEND_OFFSET 0xA00
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#define EXYNOS_WKUP_ECON_OFFSET 0xE00
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#define EXYNOS_WKUP_EMASK_OFFSET 0xF00
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#define EXYNOS_WKUP_EPEND_OFFSET 0xF40
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#define EXYNOS7_WKUP_ECON_OFFSET 0x700
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#define EXYNOS7_WKUP_EMASK_OFFSET 0x900
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#define EXYNOS7_WKUP_EPEND_OFFSET 0xA00
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#define EXYNOS_SVC_OFFSET 0xB08
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#define EXYNOSAUTO_SVC_OFFSET 0xF008
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/* helpers to access interrupt service register */
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#define EXYNOS_SVC_GROUP_SHIFT 3
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#define EXYNOS_SVC_GROUP_MASK 0x1f
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#define EXYNOS_SVC_NUM_MASK 7
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#define EXYNOS_SVC_GROUP(x) ((x >> EXYNOS_SVC_GROUP_SHIFT) & \
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EXYNOS_SVC_GROUP_MASK)
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/* Exynos specific external interrupt trigger types */
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#define EXYNOS_EINT_LEVEL_LOW 0
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#define EXYNOS_EINT_LEVEL_HIGH 1
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#define EXYNOS_EINT_EDGE_FALLING 2
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#define EXYNOS_EINT_EDGE_RISING 3
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#define EXYNOS_EINT_EDGE_BOTH 4
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#define EXYNOS_EINT_CON_MASK 0xF
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#define EXYNOS_EINT_CON_LEN 4
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#define EXYNOS_EINT_MAX_PER_BANK 8
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#define EXYNOS_EINT_NR_WKUP_EINT
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/*
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* EINT filter configuration register (on alive banks) has
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* the following layout.
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*
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* BitfieldName[PinNum][Bit:Bit]
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* FLT_EN[3][31] FLT_SEL[3][30] FLT_WIDTH[3][29:24]
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* FLT_EN[2][23] FLT_SEL[2][22] FLT_WIDTH[2][21:16]
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* FLT_EN[1][15] FLT_SEL[1][14] FLT_WIDTH[1][13:8]
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* FLT_EN[0][7] FLT_SEL[0][6] FLT_WIDTH[0][5:0]
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*
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* FLT_EN 0x0 = Disable, 0x1=Enable
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* FLT_SEL 0x0 = Analog delay filter, 0x1 Digital filter (clock count)
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* FLT_WIDTH Filtering width. Valid when FLT_SEL is 0x1
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*/
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#define EXYNOS_FLTCON_EN BIT(7)
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#define EXYNOS_FLTCON_DIGITAL BIT(6)
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#define EXYNOS_FLTCON_ANALOG (0 << 6)
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#define EXYNOS_FLTCON_LEN 8
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#define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \
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{ \
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.type = &bank_type_off, \
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.eint_type = EINT_TYPE_NONE, \
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.name = id \
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}
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#define EXYNOS_PIN_BANK_EINTG(pins, reg, id, offs) \
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{ \
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.type = &bank_type_off, \
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.eint_type = EINT_TYPE_GPIO, \
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.eint_offset = offs, \
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.name = id \
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}
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#define EXYNOS_PIN_BANK_EINTW(pins, reg, id, offs) \
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{ \
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.type = &bank_type_alive, \
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.eint_type = EINT_TYPE_WKUP, \
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.eint_offset = offs, \
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.name = id \
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}
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#define EXYNOS5433_PIN_BANK_EINTG(pins, reg, id, offs) \
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{ \
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.type = &exynos5433_bank_type_off, \
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.eint_type = EINT_TYPE_GPIO, \
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.eint_offset = offs, \
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.name = id \
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}
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#define EXYNOS5433_PIN_BANK_EINTW(pins, reg, id, offs) \
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{ \
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.type = &exynos5433_bank_type_alive, \
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.eint_type = EINT_TYPE_WKUP, \
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.eint_offset = offs, \
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.name = id \
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}
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#define EXYNOS5433_PIN_BANK_EINTW_EXT(pins, reg, id, offs, pctl_idx) \
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{ \
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.type = &exynos5433_bank_type_off, \
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.eint_type = EINT_TYPE_WKUP, \
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.eint_offset = offs, \
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.name = id, \
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.pctl_res_idx = pctl_idx, \
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} \
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#define EXYNOS7870_PIN_BANK_EINTN(pins, reg, id) \
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{ \
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.type = &exynos7870_bank_type_alive, \
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.eint_type = EINT_TYPE_NONE, \
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.name = id \
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}
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#define EXYNOS7870_PIN_BANK_EINTW(pins, reg, id, offs) \
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{ \
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.type = &exynos7870_bank_type_alive, \
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.eint_type = EINT_TYPE_WKUP, \
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.eint_offset = offs, \
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.name = id \
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}
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#define EXYNOS850_PIN_BANK_EINTN(pins, reg, id) \
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{ \
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.type = &exynos850_bank_type_alive, \
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.eint_type = EINT_TYPE_NONE, \
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.name = id \
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}
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#define EXYNOS850_PIN_BANK_EINTG(pins, reg, id, offs) \
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{ \
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.type = &exynos850_bank_type_off, \
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.eint_type = EINT_TYPE_GPIO, \
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.eint_offset = offs, \
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.name = id \
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}
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#define EXYNOS850_PIN_BANK_EINTW(pins, reg, id, offs) \
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{ \
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.type = &exynos850_bank_type_alive, \
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.eint_type = EINT_TYPE_WKUP, \
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.eint_offset = offs, \
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.name = id \
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}
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#define EXYNOS8895_PIN_BANK_EINTG(pins, reg, id, offs) \
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{ \
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.type = &exynos8895_bank_type_off, \
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.eint_type = EINT_TYPE_GPIO, \
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.eint_offset = offs, \
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.name = id \
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}
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#define EXYNOSV920_PIN_BANK_EINTG(pins, reg, id, con_offs, mask_offs, pend_offs) \
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{ \
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.type = &exynos850_bank_type_off, \
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.eint_type = EINT_TYPE_GPIO, \
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.eint_con_offset = con_offs, \
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.eint_mask_offset = mask_offs, \
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.eint_pend_offset = pend_offs, \
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.name = id \
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}
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#define EXYNOSV920_PIN_BANK_EINTW(pins, reg, id, con_offs, mask_offs, pend_offs) \
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{ \
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.type = &exynos850_bank_type_alive, \
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.eint_type = EINT_TYPE_WKUP, \
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.eint_con_offset = con_offs, \
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.eint_mask_offset = mask_offs, \
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.eint_pend_offset = pend_offs, \
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.name = id \
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}
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#define GS101_PIN_BANK_EINTG(pins, reg, id, offs, fltcon_offs) \
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{ \
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.type = &exynos850_bank_type_off, \
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.eint_type = EINT_TYPE_GPIO, \
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.eint_offset = offs, \
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.eint_fltcon_offset = fltcon_offs, \
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.name = id \
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}
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#define GS101_PIN_BANK_EINTW(pins, reg, id, offs, fltcon_offs) \
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{ \
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.type = &exynos850_bank_type_alive, \
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.eint_type = EINT_TYPE_WKUP, \
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.eint_offset = offs, \
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.eint_fltcon_offset = fltcon_offs, \
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.name = id \
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}
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/**
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* struct exynos_weint_data: irq specific data for all the wakeup interrupts
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* generated by the external wakeup interrupt controller.
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* @irq: interrupt number within the domain.
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* @bank: bank responsible for this interrupt
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*/
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struct exynos_weint_data {
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unsigned int irq;
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struct samsung_pin_bank *bank;
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};
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/**
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* struct exynos_muxed_weint_data: irq specific data for muxed wakeup interrupts
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* generated by the external wakeup interrupt controller.
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* @nr_banks: count of banks being part of the mux
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* @banks: array of banks being part of the mux
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*/
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struct exynos_muxed_weint_data {
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unsigned int nr_banks;
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struct samsung_pin_bank *banks[] __counted_by(nr_banks);
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};
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int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d);
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int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d);
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void exynosautov920_pinctrl_resume(struct samsung_pin_bank *bank);
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void exynosautov920_pinctrl_suspend(struct samsung_pin_bank *bank);
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void exynos_pinctrl_suspend(struct samsung_pin_bank *bank);
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void exynos_pinctrl_resume(struct samsung_pin_bank *bank);
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void gs101_pinctrl_suspend(struct samsung_pin_bank *bank);
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void gs101_pinctrl_resume(struct samsung_pin_bank *bank);
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struct samsung_retention_ctrl *
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exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata,
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const struct samsung_retention_data *data);
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#endif /* __PINCTRL_SAMSUNG_EXYNOS_H */
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