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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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e961ec81a3
Currently driver supports only x4 lane based functionality using tx/rx and tx2/rx2 pair of register sets. To support 8 lane functionality with PCIe3, PCIe3 related QMP PHY provides additional programming which are available as txz and rxz based register set. Hence add txz and rxz based registers usage and programming sequences. As soon as software programs the txz and rxz based register set, hardware shall "broadcast" the same settings to the tx/rx pair of registers for all the 8 lanes, which saves the effort of software programming them one by one. There might be some tx and/or rx registers on some lanes need minor tweaks, program them after programming the txz and rxz reigster set. In addition, x1e80100 uses QMP PHY ver 6.30 for PCIe Gen4 x8, hence add two new header files to reflect the new register offsets. Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konradybcio@kernel.org> Link: https://lore.kernel.org/r/20241017030412.265000-5-quic_qianyu@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
26 lines
1002 B
C
26 lines
1002 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center. All rights reserved.
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*/
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#ifndef QCOM_PHY_QMP_PCS_PCIE_V6_30_H_
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#define QCOM_PHY_QMP_PCS_PCIE_V6_30_H_
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/* Only for QMP V6_30 PHY - PCIE have different offsets than V6 */
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#define QPHY_PCIE_V6_30_PCS_POWER_STATE_CONFIG2 0x014
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#define QPHY_PCIE_V6_30_PCS_TX_RX_CONFIG 0x020
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#define QPHY_PCIE_V6_30_PCS_ENDPOINT_REFCLK_DRIVE 0x024
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#define QPHY_PCIE_V6_30_PCS_OSC_DTCT_ACTIONS 0x098
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#define QPHY_PCIE_V6_30_PCS_EQ_CONFIG1 0x0a8
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#define QPHY_PCIE_V6_30_PCS_G3_RXEQEVAL_TIME 0x0f8
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#define QPHY_PCIE_V6_30_PCS_G4_RXEQEVAL_TIME 0x0fc
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#define QPHY_PCIE_V6_30_PCS_G4_EQ_CONFIG5 0x110
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#define QPHY_PCIE_V6_30_PCS_G4_PRE_GAIN 0x164
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#define QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG1 0x184
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#define QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG3 0x18c
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#define QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG5 0x194
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#define QPHY_PCIE_V6_30_PCS_G3_FOM_EQ_CONFIG5 0x1b4
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#define QPHY_PCIE_V6_30_PCS_G4_FOM_EQ_CONFIG5 0x1c8
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#endif
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