mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-05 11:53:41 +00:00

E830 supports raw receive and generic transmit checksum offloads. Raw receive checksum support is provided by hardware calculating the checksum over the whole packet, regardless of type. The calculated checksum is provided to driver in the Rx flex descriptor. Then the driver assigns the checksum to skb->csum and sets skb->ip_summed to CHECKSUM_COMPLETE. Generic transmit checksum support is provided by hardware calculating the checksum given two offsets: the start offset to begin checksum calculation, and the offset to insert the calculated checksum in the packet. Support is advertised to the stack using NETIF_F_HW_CSUM feature. E830 has the following limitations when both generic transmit checksum offload and TCP Segmentation Offload (TSO) are enabled: 1. Inner packet header modification is not supported. This restriction includes the inability to alter TCP flags, such as the push flag. As a result, this limitation can impact the receiver's ability to coalesce packets, potentially degrading network throughput. 2. The Maximum Segment Size (MSS) is limited to 1023 bytes, which prevents support of Maximum Transmission Unit (MTU) greater than 1063 bytes. Therefore NETIF_F_HW_CSUM and NETIF_F_ALL_TSO features are mutually exclusive. NETIF_F_HW_CSUM hardware feature support is indicated but is not enabled by default. Instead, IP checksums and NETIF_F_ALL_TSO are the defaults. Enforcement of mutual exclusivity of NETIF_F_HW_CSUM and NETIF_F_ALL_TSO is done in ice_set_features(). Mutual exclusivity of IP checksums and NETIF_F_HW_CSUM is handled by netdev_fix_features(). When NETIF_F_HW_CSUM is requested the provided skb->csum_start and skb->csum_offset are passed to hardware in the Tx context descriptor generic checksum (GCS) parameters. Hardware calculates the 1's complement from skb->csum_start to the end of the packet, and inserts the result in the packet at skb->csum_offset. Co-developed-by: Alice Michael <alice.michael@intel.com> Signed-off-by: Alice Michael <alice.michael@intel.com> Co-developed-by: Eric Joyner <eric.joyner@intel.com> Signed-off-by: Eric Joyner <eric.joyner@intel.com> Signed-off-by: Paul Greenwalt <paul.greenwalt@intel.com> Reviewed-by: Simon Horman <horms@kernel.org> Tested-by: Rinitha S <sx.rinitha@intel.com> (A Contingent worker at Intel) Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com> Link: https://patch.msgid.link/20250310174502.3708121-2-anthony.l.nguyen@intel.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
588 lines
15 KiB
C
588 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright (c) 2019, Intel Corporation. */
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#include <linux/filter.h>
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#include <linux/net/intel/libie/rx.h>
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#include "ice_txrx_lib.h"
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#include "ice_eswitch.h"
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#include "ice_lib.h"
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/**
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* ice_release_rx_desc - Store the new tail and head values
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* @rx_ring: ring to bump
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* @val: new head index
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*/
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void ice_release_rx_desc(struct ice_rx_ring *rx_ring, u16 val)
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{
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u16 prev_ntu = rx_ring->next_to_use & ~0x7;
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rx_ring->next_to_use = val;
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/* update next to alloc since we have filled the ring */
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rx_ring->next_to_alloc = val;
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/* QRX_TAIL will be updated with any tail value, but hardware ignores
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* the lower 3 bits. This makes it so we only bump tail on meaningful
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* boundaries. Also, this allows us to bump tail on intervals of 8 up to
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* the budget depending on the current traffic load.
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*/
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val &= ~0x7;
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if (prev_ntu != val) {
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/* Force memory writes to complete before letting h/w
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* know there are new descriptors to fetch. (Only
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* applicable for weak-ordered memory model archs,
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* such as IA-64).
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*/
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wmb();
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writel(val, rx_ring->tail);
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}
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}
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/**
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* ice_get_rx_hash - get RX hash value from descriptor
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* @rx_desc: specific descriptor
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*
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* Returns hash, if present, 0 otherwise.
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*/
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static u32 ice_get_rx_hash(const union ice_32b_rx_flex_desc *rx_desc)
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{
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const struct ice_32b_rx_flex_desc_nic *nic_mdid;
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if (unlikely(rx_desc->wb.rxdid != ICE_RXDID_FLEX_NIC))
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return 0;
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nic_mdid = (struct ice_32b_rx_flex_desc_nic *)rx_desc;
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return le32_to_cpu(nic_mdid->rss_hash);
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}
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/**
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* ice_rx_hash_to_skb - set the hash value in the skb
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* @rx_ring: descriptor ring
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* @rx_desc: specific descriptor
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* @skb: pointer to current skb
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* @rx_ptype: the ptype value from the descriptor
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*/
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static void
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ice_rx_hash_to_skb(const struct ice_rx_ring *rx_ring,
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const union ice_32b_rx_flex_desc *rx_desc,
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struct sk_buff *skb, u16 rx_ptype)
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{
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struct libeth_rx_pt decoded;
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u32 hash;
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decoded = libie_rx_pt_parse(rx_ptype);
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if (!libeth_rx_pt_has_hash(rx_ring->netdev, decoded))
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return;
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hash = ice_get_rx_hash(rx_desc);
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if (likely(hash))
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libeth_rx_pt_set_hash(skb, hash, decoded);
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}
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/**
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* ice_rx_gcs - Set generic checksum in skb
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* @skb: skb currently being received and modified
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* @rx_desc: receive descriptor
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*/
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static void ice_rx_gcs(struct sk_buff *skb,
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const union ice_32b_rx_flex_desc *rx_desc)
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{
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const struct ice_32b_rx_flex_desc_nic *desc;
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u16 csum;
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desc = (struct ice_32b_rx_flex_desc_nic *)rx_desc;
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skb->ip_summed = CHECKSUM_COMPLETE;
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csum = (__force u16)desc->raw_csum;
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skb->csum = csum_unfold((__force __sum16)swab16(csum));
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}
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/**
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* ice_rx_csum - Indicate in skb if checksum is good
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* @ring: the ring we care about
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* @skb: skb currently being received and modified
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* @rx_desc: the receive descriptor
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* @ptype: the packet type decoded by hardware
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*
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* skb->protocol must be set before this function is called
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*/
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static void
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ice_rx_csum(struct ice_rx_ring *ring, struct sk_buff *skb,
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union ice_32b_rx_flex_desc *rx_desc, u16 ptype)
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{
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struct libeth_rx_pt decoded;
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u16 rx_status0, rx_status1;
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bool ipv4, ipv6;
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/* Start with CHECKSUM_NONE and by default csum_level = 0 */
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skb->ip_summed = CHECKSUM_NONE;
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decoded = libie_rx_pt_parse(ptype);
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if (!libeth_rx_pt_has_checksum(ring->netdev, decoded))
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return;
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rx_status0 = le16_to_cpu(rx_desc->wb.status_error0);
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rx_status1 = le16_to_cpu(rx_desc->wb.status_error1);
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if ((ring->flags & ICE_RX_FLAGS_RING_GCS) &&
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rx_desc->wb.rxdid == ICE_RXDID_FLEX_NIC &&
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(decoded.inner_prot == LIBETH_RX_PT_INNER_TCP ||
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decoded.inner_prot == LIBETH_RX_PT_INNER_UDP ||
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decoded.inner_prot == LIBETH_RX_PT_INNER_ICMP)) {
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ice_rx_gcs(skb, rx_desc);
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return;
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}
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/* check if HW has decoded the packet and checksum */
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if (!(rx_status0 & BIT(ICE_RX_FLEX_DESC_STATUS0_L3L4P_S)))
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return;
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ipv4 = libeth_rx_pt_get_ip_ver(decoded) == LIBETH_RX_PT_OUTER_IPV4;
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ipv6 = libeth_rx_pt_get_ip_ver(decoded) == LIBETH_RX_PT_OUTER_IPV6;
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if (ipv4 && (rx_status0 & (BIT(ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))) {
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ring->vsi->back->hw_rx_eipe_error++;
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return;
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}
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if (ipv4 && (rx_status0 & (BIT(ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S))))
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goto checksum_fail;
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if (ipv6 && (rx_status0 & (BIT(ICE_RX_FLEX_DESC_STATUS0_IPV6EXADD_S))))
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goto checksum_fail;
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/* check for L4 errors and handle packets that were not able to be
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* checksummed due to arrival speed
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*/
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if (rx_status0 & BIT(ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S))
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goto checksum_fail;
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/* check for outer UDP checksum error in tunneled packets */
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if ((rx_status1 & BIT(ICE_RX_FLEX_DESC_STATUS1_NAT_S)) &&
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(rx_status0 & BIT(ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S)))
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goto checksum_fail;
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/* If there is an outer header present that might contain a checksum
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* we need to bump the checksum level by 1 to reflect the fact that
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* we are indicating we validated the inner checksum.
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*/
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if (decoded.tunnel_type >= LIBETH_RX_PT_TUNNEL_IP_GRENAT)
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skb->csum_level = 1;
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skb->ip_summed = CHECKSUM_UNNECESSARY;
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return;
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checksum_fail:
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ring->vsi->back->hw_csum_rx_error++;
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}
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/**
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* ice_ptp_rx_hwts_to_skb - Put RX timestamp into skb
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* @rx_ring: Ring to get the VSI info
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* @rx_desc: Receive descriptor
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* @skb: Particular skb to send timestamp with
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*
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* The timestamp is in ns, so we must convert the result first.
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*/
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static void
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ice_ptp_rx_hwts_to_skb(struct ice_rx_ring *rx_ring,
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const union ice_32b_rx_flex_desc *rx_desc,
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struct sk_buff *skb)
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{
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u64 ts_ns = ice_ptp_get_rx_hwts(rx_desc, &rx_ring->pkt_ctx);
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skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ts_ns);
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}
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/**
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* ice_get_ptype - Read HW packet type from the descriptor
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* @rx_desc: RX descriptor
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*/
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static u16 ice_get_ptype(const union ice_32b_rx_flex_desc *rx_desc)
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{
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return le16_to_cpu(rx_desc->wb.ptype_flex_flags0) &
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ICE_RX_FLEX_DESC_PTYPE_M;
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}
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/**
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* ice_process_skb_fields - Populate skb header fields from Rx descriptor
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* @rx_ring: Rx descriptor ring packet is being transacted on
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* @rx_desc: pointer to the EOP Rx descriptor
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* @skb: pointer to current skb being populated
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*
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* This function checks the ring, descriptor, and packet information in
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* order to populate the hash, checksum, VLAN, protocol, and
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* other fields within the skb.
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*/
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void
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ice_process_skb_fields(struct ice_rx_ring *rx_ring,
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union ice_32b_rx_flex_desc *rx_desc,
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struct sk_buff *skb)
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{
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u16 ptype = ice_get_ptype(rx_desc);
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ice_rx_hash_to_skb(rx_ring, rx_desc, skb, ptype);
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/* modifies the skb - consumes the enet header */
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if (unlikely(rx_ring->flags & ICE_RX_FLAGS_MULTIDEV)) {
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struct net_device *netdev = ice_eswitch_get_target(rx_ring,
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rx_desc);
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if (ice_is_port_repr_netdev(netdev))
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ice_repr_inc_rx_stats(netdev, skb->len);
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skb->protocol = eth_type_trans(skb, netdev);
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} else {
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skb->protocol = eth_type_trans(skb, rx_ring->netdev);
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}
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ice_rx_csum(rx_ring, skb, rx_desc, ptype);
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if (rx_ring->ptp_rx)
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ice_ptp_rx_hwts_to_skb(rx_ring, rx_desc, skb);
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}
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/**
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* ice_receive_skb - Send a completed packet up the stack
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* @rx_ring: Rx ring in play
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* @skb: packet to send up
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* @vlan_tci: VLAN TCI for packet
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*
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* This function sends the completed packet (via. skb) up the stack using
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* gro receive functions (with/without VLAN tag)
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*/
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void
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ice_receive_skb(struct ice_rx_ring *rx_ring, struct sk_buff *skb, u16 vlan_tci)
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{
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if ((vlan_tci & VLAN_VID_MASK) && rx_ring->vlan_proto)
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__vlan_hwaccel_put_tag(skb, rx_ring->vlan_proto,
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vlan_tci);
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napi_gro_receive(&rx_ring->q_vector->napi, skb);
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}
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/**
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* ice_clean_xdp_tx_buf - Free and unmap XDP Tx buffer
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* @dev: device for DMA mapping
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* @tx_buf: Tx buffer to clean
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* @bq: XDP bulk flush struct
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*/
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static void
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ice_clean_xdp_tx_buf(struct device *dev, struct ice_tx_buf *tx_buf,
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struct xdp_frame_bulk *bq)
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{
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dma_unmap_single(dev, dma_unmap_addr(tx_buf, dma),
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dma_unmap_len(tx_buf, len), DMA_TO_DEVICE);
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dma_unmap_len_set(tx_buf, len, 0);
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switch (tx_buf->type) {
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case ICE_TX_BUF_XDP_TX:
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page_frag_free(tx_buf->raw_buf);
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break;
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case ICE_TX_BUF_XDP_XMIT:
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xdp_return_frame_bulk(tx_buf->xdpf, bq);
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break;
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}
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tx_buf->type = ICE_TX_BUF_EMPTY;
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}
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/**
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* ice_clean_xdp_irq - Reclaim resources after transmit completes on XDP ring
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* @xdp_ring: XDP ring to clean
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*/
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static u32 ice_clean_xdp_irq(struct ice_tx_ring *xdp_ring)
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{
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int total_bytes = 0, total_pkts = 0;
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struct device *dev = xdp_ring->dev;
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u32 ntc = xdp_ring->next_to_clean;
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struct ice_tx_desc *tx_desc;
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u32 cnt = xdp_ring->count;
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struct xdp_frame_bulk bq;
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u32 frags, xdp_tx = 0;
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u32 ready_frames = 0;
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u32 idx;
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u32 ret;
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idx = xdp_ring->tx_buf[ntc].rs_idx;
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tx_desc = ICE_TX_DESC(xdp_ring, idx);
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if (tx_desc->cmd_type_offset_bsz &
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cpu_to_le64(ICE_TX_DESC_DTYPE_DESC_DONE)) {
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if (idx >= ntc)
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ready_frames = idx - ntc + 1;
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else
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ready_frames = idx + cnt - ntc + 1;
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}
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if (unlikely(!ready_frames))
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return 0;
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ret = ready_frames;
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xdp_frame_bulk_init(&bq);
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rcu_read_lock(); /* xdp_return_frame_bulk() */
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while (ready_frames) {
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struct ice_tx_buf *tx_buf = &xdp_ring->tx_buf[ntc];
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struct ice_tx_buf *head = tx_buf;
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/* bytecount holds size of head + frags */
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total_bytes += tx_buf->bytecount;
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frags = tx_buf->nr_frags;
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total_pkts++;
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/* count head + frags */
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ready_frames -= frags + 1;
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xdp_tx++;
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ntc++;
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if (ntc == cnt)
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ntc = 0;
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for (int i = 0; i < frags; i++) {
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tx_buf = &xdp_ring->tx_buf[ntc];
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ice_clean_xdp_tx_buf(dev, tx_buf, &bq);
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ntc++;
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if (ntc == cnt)
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ntc = 0;
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}
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ice_clean_xdp_tx_buf(dev, head, &bq);
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}
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xdp_flush_frame_bulk(&bq);
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rcu_read_unlock();
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tx_desc->cmd_type_offset_bsz = 0;
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xdp_ring->next_to_clean = ntc;
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xdp_ring->xdp_tx_active -= xdp_tx;
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ice_update_tx_ring_stats(xdp_ring, total_pkts, total_bytes);
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return ret;
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}
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/**
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* __ice_xmit_xdp_ring - submit frame to XDP ring for transmission
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* @xdp: XDP buffer to be placed onto Tx descriptors
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* @xdp_ring: XDP ring for transmission
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* @frame: whether this comes from .ndo_xdp_xmit()
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*/
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int __ice_xmit_xdp_ring(struct xdp_buff *xdp, struct ice_tx_ring *xdp_ring,
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bool frame)
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{
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struct skb_shared_info *sinfo = NULL;
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u32 size = xdp->data_end - xdp->data;
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struct device *dev = xdp_ring->dev;
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u32 ntu = xdp_ring->next_to_use;
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struct ice_tx_desc *tx_desc;
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struct ice_tx_buf *tx_head;
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struct ice_tx_buf *tx_buf;
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u32 cnt = xdp_ring->count;
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void *data = xdp->data;
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u32 nr_frags = 0;
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u32 free_space;
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u32 frag = 0;
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free_space = ICE_DESC_UNUSED(xdp_ring);
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if (free_space < ICE_RING_QUARTER(xdp_ring))
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free_space += ice_clean_xdp_irq(xdp_ring);
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if (unlikely(!free_space))
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goto busy;
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if (unlikely(xdp_buff_has_frags(xdp))) {
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sinfo = xdp_get_shared_info_from_buff(xdp);
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nr_frags = sinfo->nr_frags;
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if (free_space < nr_frags + 1)
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goto busy;
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}
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tx_desc = ICE_TX_DESC(xdp_ring, ntu);
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tx_head = &xdp_ring->tx_buf[ntu];
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tx_buf = tx_head;
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for (;;) {
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dma_addr_t dma;
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dma = dma_map_single(dev, data, size, DMA_TO_DEVICE);
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if (dma_mapping_error(dev, dma))
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goto dma_unmap;
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/* record length, and DMA address */
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dma_unmap_len_set(tx_buf, len, size);
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dma_unmap_addr_set(tx_buf, dma, dma);
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if (frame) {
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tx_buf->type = ICE_TX_BUF_FRAG;
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} else {
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tx_buf->type = ICE_TX_BUF_XDP_TX;
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tx_buf->raw_buf = data;
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}
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tx_desc->buf_addr = cpu_to_le64(dma);
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tx_desc->cmd_type_offset_bsz = ice_build_ctob(0, 0, size, 0);
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ntu++;
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if (ntu == cnt)
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ntu = 0;
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if (frag == nr_frags)
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break;
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tx_desc = ICE_TX_DESC(xdp_ring, ntu);
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tx_buf = &xdp_ring->tx_buf[ntu];
|
|
|
|
data = skb_frag_address(&sinfo->frags[frag]);
|
|
size = skb_frag_size(&sinfo->frags[frag]);
|
|
frag++;
|
|
}
|
|
|
|
/* store info about bytecount and frag count in first desc */
|
|
tx_head->bytecount = xdp_get_buff_len(xdp);
|
|
tx_head->nr_frags = nr_frags;
|
|
|
|
if (frame) {
|
|
tx_head->type = ICE_TX_BUF_XDP_XMIT;
|
|
tx_head->xdpf = xdp->data_hard_start;
|
|
}
|
|
|
|
/* update last descriptor from a frame with EOP */
|
|
tx_desc->cmd_type_offset_bsz |=
|
|
cpu_to_le64(ICE_TX_DESC_CMD_EOP << ICE_TXD_QW1_CMD_S);
|
|
|
|
xdp_ring->xdp_tx_active++;
|
|
xdp_ring->next_to_use = ntu;
|
|
|
|
return ICE_XDP_TX;
|
|
|
|
dma_unmap:
|
|
for (;;) {
|
|
tx_buf = &xdp_ring->tx_buf[ntu];
|
|
dma_unmap_page(dev, dma_unmap_addr(tx_buf, dma),
|
|
dma_unmap_len(tx_buf, len), DMA_TO_DEVICE);
|
|
dma_unmap_len_set(tx_buf, len, 0);
|
|
if (tx_buf == tx_head)
|
|
break;
|
|
|
|
if (!ntu)
|
|
ntu += cnt;
|
|
ntu--;
|
|
}
|
|
return ICE_XDP_CONSUMED;
|
|
|
|
busy:
|
|
xdp_ring->ring_stats->tx_stats.tx_busy++;
|
|
|
|
return ICE_XDP_CONSUMED;
|
|
}
|
|
|
|
/**
|
|
* ice_finalize_xdp_rx - Bump XDP Tx tail and/or flush redirect map
|
|
* @xdp_ring: XDP ring
|
|
* @xdp_res: Result of the receive batch
|
|
* @first_idx: index to write from caller
|
|
*
|
|
* This function bumps XDP Tx tail and/or flush redirect map, and
|
|
* should be called when a batch of packets has been processed in the
|
|
* napi loop.
|
|
*/
|
|
void ice_finalize_xdp_rx(struct ice_tx_ring *xdp_ring, unsigned int xdp_res,
|
|
u32 first_idx)
|
|
{
|
|
struct ice_tx_buf *tx_buf = &xdp_ring->tx_buf[first_idx];
|
|
|
|
if (xdp_res & ICE_XDP_REDIR)
|
|
xdp_do_flush();
|
|
|
|
if (xdp_res & ICE_XDP_TX) {
|
|
if (static_branch_unlikely(&ice_xdp_locking_key))
|
|
spin_lock(&xdp_ring->tx_lock);
|
|
/* store index of descriptor with RS bit set in the first
|
|
* ice_tx_buf of given NAPI batch
|
|
*/
|
|
tx_buf->rs_idx = ice_set_rs_bit(xdp_ring);
|
|
ice_xdp_ring_update_tail(xdp_ring);
|
|
if (static_branch_unlikely(&ice_xdp_locking_key))
|
|
spin_unlock(&xdp_ring->tx_lock);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* ice_xdp_rx_hw_ts - HW timestamp XDP hint handler
|
|
* @ctx: XDP buff pointer
|
|
* @ts_ns: destination address
|
|
*
|
|
* Copy HW timestamp (if available) to the destination address.
|
|
*/
|
|
static int ice_xdp_rx_hw_ts(const struct xdp_md *ctx, u64 *ts_ns)
|
|
{
|
|
const struct ice_xdp_buff *xdp_ext = (void *)ctx;
|
|
|
|
*ts_ns = ice_ptp_get_rx_hwts(xdp_ext->eop_desc,
|
|
xdp_ext->pkt_ctx);
|
|
if (!*ts_ns)
|
|
return -ENODATA;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* ice_xdp_rx_hash_type - Get XDP-specific hash type from the RX descriptor
|
|
* @eop_desc: End of Packet descriptor
|
|
*/
|
|
static enum xdp_rss_hash_type
|
|
ice_xdp_rx_hash_type(const union ice_32b_rx_flex_desc *eop_desc)
|
|
{
|
|
return libie_rx_pt_parse(ice_get_ptype(eop_desc)).hash_type;
|
|
}
|
|
|
|
/**
|
|
* ice_xdp_rx_hash - RX hash XDP hint handler
|
|
* @ctx: XDP buff pointer
|
|
* @hash: hash destination address
|
|
* @rss_type: XDP hash type destination address
|
|
*
|
|
* Copy RX hash (if available) and its type to the destination address.
|
|
*/
|
|
static int ice_xdp_rx_hash(const struct xdp_md *ctx, u32 *hash,
|
|
enum xdp_rss_hash_type *rss_type)
|
|
{
|
|
const struct ice_xdp_buff *xdp_ext = (void *)ctx;
|
|
|
|
*hash = ice_get_rx_hash(xdp_ext->eop_desc);
|
|
*rss_type = ice_xdp_rx_hash_type(xdp_ext->eop_desc);
|
|
if (!likely(*hash))
|
|
return -ENODATA;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* ice_xdp_rx_vlan_tag - VLAN tag XDP hint handler
|
|
* @ctx: XDP buff pointer
|
|
* @vlan_proto: destination address for VLAN protocol
|
|
* @vlan_tci: destination address for VLAN TCI
|
|
*
|
|
* Copy VLAN tag (if was stripped) and corresponding protocol
|
|
* to the destination address.
|
|
*/
|
|
static int ice_xdp_rx_vlan_tag(const struct xdp_md *ctx, __be16 *vlan_proto,
|
|
u16 *vlan_tci)
|
|
{
|
|
const struct ice_xdp_buff *xdp_ext = (void *)ctx;
|
|
|
|
*vlan_proto = xdp_ext->pkt_ctx->vlan_proto;
|
|
if (!*vlan_proto)
|
|
return -ENODATA;
|
|
|
|
*vlan_tci = ice_get_vlan_tci(xdp_ext->eop_desc);
|
|
if (!*vlan_tci)
|
|
return -ENODATA;
|
|
|
|
return 0;
|
|
}
|
|
|
|
const struct xdp_metadata_ops ice_xdp_md_ops = {
|
|
.xmo_rx_timestamp = ice_xdp_rx_hw_ts,
|
|
.xmo_rx_hash = ice_xdp_rx_hash,
|
|
.xmo_rx_vlan_tag = ice_xdp_rx_vlan_tag,
|
|
};
|