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b3b26c983a
Instead of multiple comments, use designated initializers for TSPLL consts. Adjust ice_tspll_params_e82x fields sizes. Reviewed-by: Michal Kubiak <michal.kubiak@intel.com> Reviewed-by: Milena Olech <milena.olech@intel.com> Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com> Tested-by: Rinitha S <sx.rinitha@intel.com> (A Contingent worker at Intel) Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
32 lines
820 B
C
32 lines
820 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2025, Intel Corporation. */
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#ifndef _ICE_TSPLL_H_
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#define _ICE_TSPLL_H_
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/**
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* struct ice_tspll_params_e82x - E82X TSPLL parameters
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* @refclk_pre_div: Reference clock pre-divisor
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* @post_pll_div: Post PLL divisor
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* @feedback_div: Feedback divisor
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* @frac_n_div: Fractional divisor
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*
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* Clock Generation Unit parameters used to program the PLL based on the
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* selected TIME_REF/TCXO frequency.
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*/
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struct ice_tspll_params_e82x {
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u8 refclk_pre_div;
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u8 post_pll_div;
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u8 feedback_div;
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u32 frac_n_div;
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};
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#define ICE_TSPLL_CK_REFCLKFREQ_E825 0x1F
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#define ICE_TSPLL_NDIVRATIO_E825 5
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#define ICE_TSPLL_FBDIV_INTGR_E825 256
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int ice_tspll_cfg_pps_out_e825c(struct ice_hw *hw, bool enable);
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int ice_tspll_init(struct ice_hw *hw);
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#endif /* _ICE_TSPLL_H_ */
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