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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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5bcea24133
Implement reference sync input pin get/set callbacks, allow user space control over dpll pin pairs capable of reference sync support. Reviewed-by: Milena Olech <milena.olech@intel.com> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com> Link: https://patch.msgid.link/20250626135219.1769350-4-arkadiusz.kubalewski@intel.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
146 lines
4.2 KiB
C
146 lines
4.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2022, Intel Corporation. */
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#ifndef _ICE_DPLL_H_
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#define _ICE_DPLL_H_
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#include "ice.h"
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#define ICE_DPLL_RCLK_NUM_MAX 4
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/**
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* enum ice_dpll_pin_sw - enumerate ice software pin indices:
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* @ICE_DPLL_PIN_SW_1_IDX: index of first SW pin
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* @ICE_DPLL_PIN_SW_2_IDX: index of second SW pin
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* @ICE_DPLL_PIN_SW_NUM: number of SW pins in pair
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*/
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enum ice_dpll_pin_sw {
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ICE_DPLL_PIN_SW_1_IDX,
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ICE_DPLL_PIN_SW_2_IDX,
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ICE_DPLL_PIN_SW_NUM
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};
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/** ice_dpll_pin - store info about pins
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* @pin: dpll pin structure
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* @pf: pointer to pf, which has registered the dpll_pin
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* @idx: ice pin private idx
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* @num_parents: hols number of parent pins
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* @parent_idx: hold indexes of parent pins
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* @flags: pin flags returned from HW
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* @state: state of a pin
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* @prop: pin properties
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* @freq: current frequency of a pin
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* @phase_adjust: current phase adjust value
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* @phase_offset: monitored phase offset value
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* @ref_sync: store id of reference sync pin
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*/
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struct ice_dpll_pin {
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struct dpll_pin *pin;
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struct ice_pf *pf;
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u8 idx;
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u8 num_parents;
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u8 parent_idx[ICE_DPLL_RCLK_NUM_MAX];
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u8 flags[ICE_DPLL_RCLK_NUM_MAX];
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u8 state[ICE_DPLL_RCLK_NUM_MAX];
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struct dpll_pin_properties prop;
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u32 freq;
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s32 phase_adjust;
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struct ice_dpll_pin *input;
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struct ice_dpll_pin *output;
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enum dpll_pin_direction direction;
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s64 phase_offset;
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u8 status;
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u8 ref_sync;
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bool active;
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bool hidden;
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};
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/** ice_dpll - store info required for DPLL control
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* @dpll: pointer to dpll dev
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* @pf: pointer to pf, which has registered the dpll_device
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* @dpll_idx: index of dpll on the NIC
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* @input_idx: currently selected input index
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* @prev_input_idx: previously selected input index
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* @ref_state: state of dpll reference signals
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* @eec_mode: eec_mode dpll is configured for
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* @phase_offset: phase offset of active pin vs dpll signal
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* @prev_phase_offset: previous phase offset of active pin vs dpll signal
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* @input_prio: priorities of each input
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* @dpll_state: current dpll sync state
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* @prev_dpll_state: last dpll sync state
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* @phase_offset_monitor_period: period for phase offset monitor read frequency
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* @active_input: pointer to active input pin
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* @prev_input: pointer to previous active input pin
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* @ops: holds the registered ops
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*/
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struct ice_dpll {
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struct dpll_device *dpll;
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struct ice_pf *pf;
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u8 dpll_idx;
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u8 input_idx;
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u8 prev_input_idx;
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u8 ref_state;
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u8 eec_mode;
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s64 phase_offset;
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s64 prev_phase_offset;
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u8 *input_prio;
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enum dpll_lock_status dpll_state;
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enum dpll_lock_status prev_dpll_state;
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enum dpll_mode mode;
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u32 phase_offset_monitor_period;
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struct dpll_pin *active_input;
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struct dpll_pin *prev_input;
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const struct dpll_device_ops *ops;
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};
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/** ice_dplls - store info required for CCU (clock controlling unit)
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* @kworker: periodic worker
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* @work: periodic work
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* @lock: locks access to configuration of a dpll
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* @eec: pointer to EEC dpll dev
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* @pps: pointer to PPS dpll dev
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* @inputs: input pins pointer
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* @outputs: output pins pointer
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* @rclk: recovered pins pointer
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* @num_inputs: number of input pins available on dpll
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* @num_outputs: number of output pins available on dpll
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* @cgu_state_acq_err_num: number of errors returned during periodic work
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* @base_rclk_idx: idx of first pin used for clock revocery pins
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* @clock_id: clock_id of dplls
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* @input_phase_adj_max: max phase adjust value for an input pins
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* @output_phase_adj_max: max phase adjust value for an output pins
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* @periodic_counter: counter of periodic work executions
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*/
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struct ice_dplls {
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struct kthread_worker *kworker;
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struct kthread_delayed_work work;
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struct mutex lock;
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struct ice_dpll eec;
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struct ice_dpll pps;
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struct ice_dpll_pin *inputs;
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struct ice_dpll_pin *outputs;
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struct ice_dpll_pin sma[ICE_DPLL_PIN_SW_NUM];
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struct ice_dpll_pin ufl[ICE_DPLL_PIN_SW_NUM];
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struct ice_dpll_pin rclk;
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u8 num_inputs;
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u8 num_outputs;
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u8 sma_data;
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u8 base_rclk_idx;
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int cgu_state_acq_err_num;
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u64 clock_id;
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s32 input_phase_adj_max;
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s32 output_phase_adj_max;
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u32 periodic_counter;
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bool generic;
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};
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#if IS_ENABLED(CONFIG_PTP_1588_CLOCK)
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void ice_dpll_init(struct ice_pf *pf);
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void ice_dpll_deinit(struct ice_pf *pf);
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#else
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static inline void ice_dpll_init(struct ice_pf *pf) { }
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static inline void ice_dpll_deinit(struct ice_pf *pf) { }
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#endif
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#endif
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