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The live migration driver will need to save and restore the Tx queue context state from the hardware registers. This state contains both static fields which do not change during Tx traffic as well as dynamic fields which may change during Tx traffic. Unlike the Rx context, the Tx queue context is accessed indirectly from GLCOMM_QTX_CNTX_CTL and GLCOMM_QTX_CNTX_DATA registers. These registers are shared by multiple PFs on the same PCIe card. Multiple PFs cannot safely access the registers simultaneously, and there is no hardware semaphore or logic to control access. To handle this, introduce the txq_ctx_lock to the ice_adapter structure. This is similar to the ptp_gltsyn_time_lock. All PFs on the same adapter share this structure, and use it to serialize access to the registers to prevent error. Add a new functions to get and set the Tx queue context through the GLCOMM_QTX_CNTX_CTL interface. The hardware context values are stored in the registers using the same packed format as the Admin Queue buffer. The hardware buffer is 40 bytes wide, as it contains an additional 18 bytes of internal state not sent with the Admin Queue buffer. For this reason, a separate typedef and packing function must be used. We can share the same packed fields definitions because we never need to unpack the internal state. This is preferred, as it ensures the internal state is zero'd when writing into HW, and avoids issues with reading by u32 registers into a buffer of 22 bytes in length. Thanks to the typedefs, misuse of the API with the wrong size buffer can easily be caught at compile time. Note reading this data from hardware is essential because the current Tx queue context may be different from the context as initially programmed by the driver during VF initialization. When migrating a VF we must ensure the target VF has identical context as the source VF did. Co-developed-by: Yahui Cao <yahui.cao@intel.com> Signed-off-by: Yahui Cao <yahui.cao@intel.com> Signed-off-by: Jacob Keller <jacob.e.keller@intel.com> Reviewed-by: Madhu Chittim <madhu.chittim@intel.com> Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com> Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
54 lines
1.5 KiB
C
54 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* SPDX-FileCopyrightText: Copyright Red Hat */
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#ifndef _ICE_ADAPTER_H_
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#define _ICE_ADAPTER_H_
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#include <linux/types.h>
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#include <linux/spinlock_types.h>
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#include <linux/refcount_types.h>
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struct pci_dev;
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struct ice_pf;
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/**
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* struct ice_port_list - data used to store the list of adapter ports
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*
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* This structure contains data used to maintain a list of adapter ports
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*
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* @ports: list of ports
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* @lock: protect access to the ports list
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*/
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struct ice_port_list {
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struct list_head ports;
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/* To synchronize the ports list operations */
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struct mutex lock;
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};
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/**
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* struct ice_adapter - PCI adapter resources shared across PFs
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* @refcount: Reference count. struct ice_pf objects hold the references.
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* @ptp_gltsyn_time_lock: Spinlock protecting access to the GLTSYN_TIME
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* register of the PTP clock.
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* @txq_ctx_lock: Spinlock protecting access to the GLCOMM_QTX_CNTX_CTL register
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* @ctrl_pf: Control PF of the adapter
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* @ports: Ports list
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* @device_serial_number: DSN cached for collision detection on 32bit systems
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*/
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struct ice_adapter {
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refcount_t refcount;
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/* For access to the GLTSYN_TIME register */
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spinlock_t ptp_gltsyn_time_lock;
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/* For access to GLCOMM_QTX_CNTX_CTL register */
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spinlock_t txq_ctx_lock;
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struct ice_pf *ctrl_pf;
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struct ice_port_list ports;
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u64 device_serial_number;
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};
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struct ice_adapter *ice_adapter_get(struct pci_dev *pdev);
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void ice_adapter_put(struct pci_dev *pdev);
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#endif /* _ICE_ADAPTER_H */
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