mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-01 06:39:05 +00:00
17fcb3dc12
This is [1/3] part of hinic3 Ethernet driver initial submission. With this patch hinic3 is a valid kernel module but non-functional driver. The driver parts contained in this patch: Module initialization. PCI driver registration but with empty id_table. Auxiliary driver registration. Net device_ops registration but open/stop are empty stubs. tx/rx logic. All major data structures of the driver are fully introduced with the code that uses them but without their initialization code that requires management interface with the hw. Co-developed-by: Xin Guo <guoxin09@huawei.com> Signed-off-by: Xin Guo <guoxin09@huawei.com> Signed-off-by: Fan Gong <gongfan1@huawei.com> Co-developed-by: Gur Stavi <gur.stavi@huawei.com> Signed-off-by: Gur Stavi <gur.stavi@huawei.com> Link: https://patch.msgid.link/76a137ffdfe115c737c2c224f0c93b60ba53cc16.1747736586.git.gur.stavi@huawei.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
114 lines
3.0 KiB
C
114 lines
3.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) Huawei Technologies Co., Ltd. 2025. All rights reserved. */
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#ifndef _HINIC3_HW_INTF_H_
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#define _HINIC3_HW_INTF_H_
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#include <linux/bits.h>
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#include <linux/types.h>
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#define MGMT_MSG_CMD_OP_SET 1
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#define MGMT_MSG_CMD_OP_GET 0
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#define MGMT_STATUS_PF_SET_VF_ALREADY 0x4
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#define MGMT_STATUS_EXIST 0x6
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#define MGMT_STATUS_CMD_UNSUPPORTED 0xFF
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#define MGMT_MSG_POLLING_TIMEOUT 0
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struct mgmt_msg_head {
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u8 status;
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u8 version;
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u8 rsvd0[6];
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};
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struct mgmt_msg_params {
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const void *buf_in;
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u32 in_size;
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void *buf_out;
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u32 expected_out_size;
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u32 timeout_ms;
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};
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/* CMDQ MODULE_TYPE */
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enum mgmt_mod_type {
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/* HW communication module */
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MGMT_MOD_COMM = 0,
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/* L2NIC module */
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MGMT_MOD_L2NIC = 1,
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/* Configuration module */
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MGMT_MOD_CFGM = 7,
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MGMT_MOD_HILINK = 14,
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};
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static inline void mgmt_msg_params_init_default(struct mgmt_msg_params *msg_params,
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void *inout_buf, u32 buf_size)
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{
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msg_params->buf_in = inout_buf;
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msg_params->buf_out = inout_buf;
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msg_params->in_size = buf_size;
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msg_params->expected_out_size = buf_size;
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msg_params->timeout_ms = 0;
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}
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/* COMM Commands between Driver to fw */
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enum comm_cmd {
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/* Commands for clearing FLR and resources */
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COMM_CMD_FUNC_RESET = 0,
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COMM_CMD_FEATURE_NEGO = 1,
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COMM_CMD_FLUSH_DOORBELL = 2,
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COMM_CMD_START_FLUSH = 3,
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COMM_CMD_GET_GLOBAL_ATTR = 5,
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COMM_CMD_SET_FUNC_SVC_USED_STATE = 7,
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/* Driver Configuration Commands */
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COMM_CMD_SET_CMDQ_CTXT = 20,
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COMM_CMD_SET_VAT = 21,
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COMM_CMD_CFG_PAGESIZE = 22,
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COMM_CMD_CFG_MSIX_CTRL_REG = 23,
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COMM_CMD_SET_CEQ_CTRL_REG = 24,
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COMM_CMD_SET_DMA_ATTR = 25,
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};
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enum comm_func_reset_bits {
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COMM_FUNC_RESET_BIT_FLUSH = BIT(0),
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COMM_FUNC_RESET_BIT_MQM = BIT(1),
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COMM_FUNC_RESET_BIT_SMF = BIT(2),
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COMM_FUNC_RESET_BIT_PF_BW_CFG = BIT(3),
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COMM_FUNC_RESET_BIT_COMM = BIT(10),
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/* clear mbox and aeq, The COMM_FUNC_RESET_BIT_COMM bit must be set */
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COMM_FUNC_RESET_BIT_COMM_MGMT_CH = BIT(11),
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/* clear cmdq and ceq, The COMM_FUNC_RESET_BIT_COMM bit must be set */
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COMM_FUNC_RESET_BIT_COMM_CMD_CH = BIT(12),
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COMM_FUNC_RESET_BIT_NIC = BIT(13),
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};
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struct comm_cmd_func_reset {
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struct mgmt_msg_head head;
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u16 func_id;
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u16 rsvd1[3];
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u64 reset_flag;
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};
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#define COMM_MAX_FEATURE_QWORD 4
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struct comm_cmd_feature_nego {
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struct mgmt_msg_head head;
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u16 func_id;
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u8 opcode;
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u8 rsvd;
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u64 s_feature[COMM_MAX_FEATURE_QWORD];
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};
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/* Services supported by HW. HW uses these values when delivering events.
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* HW supports multiple services that are not yet supported by driver
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* (e.g. RoCE).
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*/
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enum hinic3_service_type {
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HINIC3_SERVICE_T_NIC = 0,
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/* MAX is only used by SW for array sizes. */
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HINIC3_SERVICE_T_MAX = 1,
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};
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#endif
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