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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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1d1e564fce
The CRU block on the Renesas RZ/G3E SoC is similar to the one found on the Renesas RZ/G2L SoC, with the following differences: - Additional registers rzg3e_cru_regs. - A different irq handler rzg3e_cru_irq. - A different rzg3e_cru_csi2_setup. - A different max input width. - Additional stride register. Introduce rzg3e_cru_info struct to handle differences between RZ/G2L and RZ/G3E and related RZ/G3E functions: - rzg3e_cru_enable_interrupts() - rzg3e_cru_enable_interrupts() - rz3e_fifo_empty() - rzg3e_cru_csi2_setup() - rzg3e_cru_get_current_slot() Add then support for the RZ/G3E SoC CRU block with the new compatible string "renesas,r9a09g047-cru". Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Link: https://lore.kernel.org/r/20250411170624.472257-18-tommaso.merciai.xr@bp.renesas.com Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
112 lines
3.8 KiB
C
112 lines
3.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* rzg2l-cru-regs.h--RZ/G2L (and alike SoCs) CRU Registers Definitions
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*
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* Copyright (C) 2024 Renesas Electronics Corp.
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*/
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#ifndef __RZG2L_CRU_REGS_H__
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#define __RZG2L_CRU_REGS_H__
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/* HW CRU Registers Definition */
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#define CRUnCTRL_VINSEL(x) ((x) << 0)
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#define CRUnIE_EFE BIT(17)
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#define CRUnIE2_FSxE(x) BIT(((x) * 3))
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#define CRUnIE2_FExE(x) BIT(((x) * 3) + 1)
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#define CRUnINTS_SFS BIT(16)
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#define CRUnINTS2_FSxS(x) BIT(((x) * 3))
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#define CRUnRST_VRESETN BIT(0)
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/* Memory Bank Base Address (Lower) Register for CRU Image Data */
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#define AMnMBxADDRL(x) (AMnMB1ADDRL + (x) * 2)
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/* Memory Bank Base Address (Higher) Register for CRU Image Data */
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#define AMnMBxADDRH(x) (AMnMB1ADDRH + (x) * 2)
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#define AMnMBVALID_MBVALID(x) GENMASK(x, 0)
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#define AMnMBS_MBSTS 0x7
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#define AMnAXIATTR_AXILEN_MASK GENMASK(3, 0)
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#define AMnAXIATTR_AXILEN (0xf)
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#define AMnFIFOPNTR_FIFOWPNTR GENMASK(7, 0)
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#define AMnFIFOPNTR_FIFOWPNTR_B0 AMnFIFOPNTR_FIFOWPNTR
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#define AMnFIFOPNTR_FIFOWPNTR_B1 GENMASK(15, 8)
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#define AMnFIFOPNTR_FIFORPNTR_Y GENMASK(23, 16)
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#define AMnFIFOPNTR_FIFORPNTR_B0 AMnFIFOPNTR_FIFORPNTR_Y
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#define AMnFIFOPNTR_FIFORPNTR_B1 GENMASK(31, 24)
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#define AMnIS_IS_MASK GENMASK(14, 7)
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#define AMnIS_IS(x) ((x) << 7)
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#define AMnAXISTP_AXI_STOP BIT(0)
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#define AMnAXISTPACK_AXI_STOP_ACK BIT(0)
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#define ICnEN_ICEN BIT(0)
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#define ICnSVC_SVC0(x) (x)
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#define ICnSVC_SVC1(x) ((x) << 4)
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#define ICnSVC_SVC2(x) ((x) << 8)
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#define ICnSVC_SVC3(x) ((x) << 12)
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#define ICnMC_CSCTHR BIT(5)
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#define ICnMC_INF(x) ((x) << 16)
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#define ICnMC_VCSEL(x) ((x) << 22)
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#define ICnMC_INF_MASK GENMASK(21, 16)
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#define ICnMS_IA BIT(2)
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#define ICnDMR_YCMODE_UYVY (1 << 4)
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enum rzg2l_cru_common_regs {
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CRUnCTRL, /* CRU Control */
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CRUnIE, /* CRU Interrupt Enable */
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CRUnIE2, /* CRU Interrupt Enable(2) */
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CRUnINTS, /* CRU Interrupt Status */
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CRUnINTS2, /* CRU Interrupt Status(2) */
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CRUnRST, /* CRU Reset */
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AMnMB1ADDRL, /* Bank 1 Address (Lower) for CRU Image Data */
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AMnMB1ADDRH, /* Bank 1 Address (Higher) for CRU Image Data */
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AMnMB2ADDRL, /* Bank 2 Address (Lower) for CRU Image Data */
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AMnMB2ADDRH, /* Bank 2 Address (Higher) for CRU Image Data */
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AMnMB3ADDRL, /* Bank 3 Address (Lower) for CRU Image Data */
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AMnMB3ADDRH, /* Bank 3 Address (Higher) for CRU Image Data */
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AMnMB4ADDRL, /* Bank 4 Address (Lower) for CRU Image Data */
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AMnMB4ADDRH, /* Bank 4 Address (Higher) for CRU Image Data */
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AMnMB5ADDRL, /* Bank 5 Address (Lower) for CRU Image Data */
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AMnMB5ADDRH, /* Bank 5 Address (Higher) for CRU Image Data */
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AMnMB6ADDRL, /* Bank 6 Address (Lower) for CRU Image Data */
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AMnMB6ADDRH, /* Bank 6 Address (Higher) for CRU Image Data */
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AMnMB7ADDRL, /* Bank 7 Address (Lower) for CRU Image Data */
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AMnMB7ADDRH, /* Bank 7 Address (Higher) for CRU Image Data */
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AMnMB8ADDRL, /* Bank 8 Address (Lower) for CRU Image Data */
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AMnMB8ADDRH, /* Bank 8 Address (Higher) for CRU Image Data */
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AMnMBVALID, /* Memory Bank Enable for CRU Image Data */
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AMnMBS, /* Memory Bank Status for CRU Image Data */
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AMnMADRSL, /* VD Memory Address Lower Status Register */
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AMnMADRSH, /* VD Memory Address Higher Status Register */
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AMnAXIATTR, /* AXI Master Transfer Setting Register for CRU Image Data */
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AMnFIFOPNTR, /* AXI Master FIFO Pointer for CRU Image Data */
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AMnAXISTP, /* AXI Master Transfer Stop for CRU Image Data */
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AMnAXISTPACK, /* AXI Master Transfer Stop Status for CRU Image Data */
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AMnIS, /* Image Stride Setting Register */
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ICnEN, /* CRU Image Processing Enable */
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ICnSVCNUM, /* CRU SVC Number Register */
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ICnSVC, /* CRU VC Select Register */
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ICnMC, /* CRU Image Processing Main Control */
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ICnIPMC_C0, /* CRU Image Converter Main Control 0 */
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ICnMS, /* CRU Module Status */
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ICnDMR, /* CRU Data Output Mode */
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RZG2L_CRU_MAX_REG,
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};
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#endif /* __RZG2L_CRU_REGS_H__ */
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