mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-02 16:44:59 +00:00
caf2055487
During reconfig, the firmware sends the resolution aligned to 8 bytes.
If the driver sends the same resolution back to the firmware the resolution
will be aligned to 16 bytes not 8.
The alignment mismatch would then subsequently cause the firmware to
send another redundant sequence change event.
Fix this by not setting the resolution property during reconfig.
Cc: stable@vger.kernel.org
Fixes: 3a19d7b9e0 ("media: iris: implement set properties to firmware during streamon")
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK
Signed-off-by: Dikshita Agarwal <quic_dikshita@quicinc.com>
Tested-by: Vikash Garodia <quic_vgarodia@quicinc.com> # on sa8775p-ride
Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
277 lines
7.3 KiB
C
277 lines
7.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <media/v4l2-mem2mem.h>
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#include "iris_instance.h"
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static bool iris_allow_inst_state_change(struct iris_inst *inst,
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enum iris_inst_state req_state)
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{
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switch (inst->state) {
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case IRIS_INST_INIT:
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if (req_state == IRIS_INST_INPUT_STREAMING ||
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req_state == IRIS_INST_OUTPUT_STREAMING ||
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req_state == IRIS_INST_DEINIT)
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return true;
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return false;
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case IRIS_INST_INPUT_STREAMING:
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if (req_state == IRIS_INST_INIT ||
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req_state == IRIS_INST_STREAMING ||
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req_state == IRIS_INST_DEINIT)
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return true;
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return false;
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case IRIS_INST_OUTPUT_STREAMING:
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if (req_state == IRIS_INST_INIT ||
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req_state == IRIS_INST_STREAMING ||
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req_state == IRIS_INST_DEINIT)
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return true;
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return false;
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case IRIS_INST_STREAMING:
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if (req_state == IRIS_INST_INPUT_STREAMING ||
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req_state == IRIS_INST_OUTPUT_STREAMING ||
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req_state == IRIS_INST_DEINIT)
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return true;
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return false;
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case IRIS_INST_DEINIT:
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if (req_state == IRIS_INST_INIT)
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return true;
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return false;
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default:
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return false;
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}
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}
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int iris_inst_change_state(struct iris_inst *inst,
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enum iris_inst_state request_state)
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{
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if (inst->state == IRIS_INST_ERROR)
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return 0;
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if (inst->state == request_state)
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return 0;
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if (request_state == IRIS_INST_ERROR)
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goto change_state;
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if (!iris_allow_inst_state_change(inst, request_state))
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return -EINVAL;
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change_state:
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inst->state = request_state;
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dev_dbg(inst->core->dev, "state changed from %x to %x\n",
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inst->state, request_state);
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return 0;
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}
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int iris_inst_state_change_streamon(struct iris_inst *inst, u32 plane)
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{
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enum iris_inst_state new_state = IRIS_INST_ERROR;
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if (V4L2_TYPE_IS_OUTPUT(plane)) {
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if (inst->state == IRIS_INST_INIT)
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new_state = IRIS_INST_INPUT_STREAMING;
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else if (inst->state == IRIS_INST_OUTPUT_STREAMING)
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new_state = IRIS_INST_STREAMING;
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} else if (V4L2_TYPE_IS_CAPTURE(plane)) {
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if (inst->state == IRIS_INST_INIT)
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new_state = IRIS_INST_OUTPUT_STREAMING;
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else if (inst->state == IRIS_INST_INPUT_STREAMING)
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new_state = IRIS_INST_STREAMING;
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}
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return iris_inst_change_state(inst, new_state);
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}
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int iris_inst_state_change_streamoff(struct iris_inst *inst, u32 plane)
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{
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enum iris_inst_state new_state = IRIS_INST_ERROR;
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if (V4L2_TYPE_IS_OUTPUT(plane)) {
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if (inst->state == IRIS_INST_INPUT_STREAMING)
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new_state = IRIS_INST_INIT;
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else if (inst->state == IRIS_INST_STREAMING)
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new_state = IRIS_INST_OUTPUT_STREAMING;
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} else if (V4L2_TYPE_IS_CAPTURE(plane)) {
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if (inst->state == IRIS_INST_OUTPUT_STREAMING)
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new_state = IRIS_INST_INIT;
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else if (inst->state == IRIS_INST_STREAMING)
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new_state = IRIS_INST_INPUT_STREAMING;
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}
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return iris_inst_change_state(inst, new_state);
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}
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static bool iris_inst_allow_sub_state(struct iris_inst *inst, enum iris_inst_sub_state sub_state)
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{
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if (!sub_state)
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return true;
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switch (inst->state) {
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case IRIS_INST_INIT:
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if (sub_state & IRIS_INST_SUB_LOAD_RESOURCES)
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return true;
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return false;
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case IRIS_INST_INPUT_STREAMING:
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if (sub_state & (IRIS_INST_SUB_FIRST_IPSC | IRIS_INST_SUB_DRC |
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IRIS_INST_SUB_DRAIN | IRIS_INST_SUB_INPUT_PAUSE))
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return true;
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return false;
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case IRIS_INST_OUTPUT_STREAMING:
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if (sub_state & (IRIS_INST_SUB_DRC_LAST |
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IRIS_INST_SUB_DRAIN_LAST | IRIS_INST_SUB_OUTPUT_PAUSE))
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return true;
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return false;
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case IRIS_INST_STREAMING:
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if (sub_state & (IRIS_INST_SUB_DRC | IRIS_INST_SUB_DRAIN |
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IRIS_INST_SUB_DRC_LAST | IRIS_INST_SUB_DRAIN_LAST |
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IRIS_INST_SUB_INPUT_PAUSE | IRIS_INST_SUB_OUTPUT_PAUSE))
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return true;
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return false;
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case IRIS_INST_DEINIT:
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if (sub_state & (IRIS_INST_SUB_DRC | IRIS_INST_SUB_DRAIN |
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IRIS_INST_SUB_DRC_LAST | IRIS_INST_SUB_DRAIN_LAST |
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IRIS_INST_SUB_INPUT_PAUSE | IRIS_INST_SUB_OUTPUT_PAUSE))
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return true;
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return false;
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default:
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return false;
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}
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}
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int iris_inst_change_sub_state(struct iris_inst *inst,
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enum iris_inst_sub_state clear_sub_state,
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enum iris_inst_sub_state set_sub_state)
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{
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enum iris_inst_sub_state prev_sub_state;
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if (inst->state == IRIS_INST_ERROR)
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return 0;
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if (!clear_sub_state && !set_sub_state)
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return 0;
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if ((clear_sub_state & set_sub_state) ||
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set_sub_state > IRIS_INST_MAX_SUB_STATE_VALUE ||
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clear_sub_state > IRIS_INST_MAX_SUB_STATE_VALUE)
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return -EINVAL;
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prev_sub_state = inst->sub_state;
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if (!iris_inst_allow_sub_state(inst, set_sub_state))
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return -EINVAL;
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inst->sub_state |= set_sub_state;
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inst->sub_state &= ~clear_sub_state;
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if (inst->sub_state != prev_sub_state)
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dev_dbg(inst->core->dev, "sub_state changed from %x to %x\n",
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prev_sub_state, inst->sub_state);
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return 0;
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}
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int iris_inst_sub_state_change_drc(struct iris_inst *inst)
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{
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enum iris_inst_sub_state set_sub_state = 0;
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if (inst->sub_state & IRIS_INST_SUB_DRC)
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return -EINVAL;
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if (inst->state == IRIS_INST_INPUT_STREAMING ||
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inst->state == IRIS_INST_INIT)
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set_sub_state = IRIS_INST_SUB_FIRST_IPSC | IRIS_INST_SUB_INPUT_PAUSE;
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else
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set_sub_state = IRIS_INST_SUB_DRC | IRIS_INST_SUB_INPUT_PAUSE;
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return iris_inst_change_sub_state(inst, 0, set_sub_state);
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}
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int iris_inst_sub_state_change_drain_last(struct iris_inst *inst)
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{
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enum iris_inst_sub_state set_sub_state;
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if (inst->sub_state & IRIS_INST_SUB_DRAIN_LAST)
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return -EINVAL;
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if (!(inst->sub_state & IRIS_INST_SUB_DRAIN))
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return -EINVAL;
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set_sub_state = IRIS_INST_SUB_DRAIN_LAST | IRIS_INST_SUB_OUTPUT_PAUSE;
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return iris_inst_change_sub_state(inst, 0, set_sub_state);
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}
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int iris_inst_sub_state_change_drc_last(struct iris_inst *inst)
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{
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enum iris_inst_sub_state set_sub_state;
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if (inst->sub_state & IRIS_INST_SUB_DRC_LAST)
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return -EINVAL;
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if (!(inst->sub_state & IRIS_INST_SUB_DRC) ||
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!(inst->sub_state & IRIS_INST_SUB_INPUT_PAUSE))
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return -EINVAL;
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if (inst->sub_state & IRIS_INST_SUB_FIRST_IPSC)
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return 0;
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set_sub_state = IRIS_INST_SUB_DRC_LAST | IRIS_INST_SUB_OUTPUT_PAUSE;
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return iris_inst_change_sub_state(inst, 0, set_sub_state);
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}
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int iris_inst_sub_state_change_pause(struct iris_inst *inst, u32 plane)
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{
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enum iris_inst_sub_state set_sub_state;
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if (V4L2_TYPE_IS_OUTPUT(plane)) {
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if (inst->sub_state & IRIS_INST_SUB_DRC &&
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!(inst->sub_state & IRIS_INST_SUB_DRC_LAST))
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return -EINVAL;
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if (inst->sub_state & IRIS_INST_SUB_DRAIN &&
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!(inst->sub_state & IRIS_INST_SUB_DRAIN_LAST))
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return -EINVAL;
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set_sub_state = IRIS_INST_SUB_INPUT_PAUSE;
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} else {
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set_sub_state = IRIS_INST_SUB_OUTPUT_PAUSE;
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}
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return iris_inst_change_sub_state(inst, 0, set_sub_state);
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}
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bool iris_drc_pending(struct iris_inst *inst)
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{
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return inst->sub_state & IRIS_INST_SUB_DRC &&
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inst->sub_state & IRIS_INST_SUB_DRC_LAST;
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}
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static inline bool iris_drain_pending(struct iris_inst *inst)
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{
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return inst->sub_state & IRIS_INST_SUB_DRAIN &&
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inst->sub_state & IRIS_INST_SUB_DRAIN_LAST;
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}
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bool iris_allow_cmd(struct iris_inst *inst, u32 cmd)
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{
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struct vb2_queue *src_q = v4l2_m2m_get_src_vq(inst->m2m_ctx);
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struct vb2_queue *dst_q = v4l2_m2m_get_dst_vq(inst->m2m_ctx);
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if (cmd == V4L2_DEC_CMD_START) {
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if (vb2_is_streaming(src_q) || vb2_is_streaming(dst_q))
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if (iris_drc_pending(inst) || iris_drain_pending(inst))
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return true;
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} else if (cmd == V4L2_DEC_CMD_STOP) {
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if (vb2_is_streaming(src_q))
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if (inst->sub_state != IRIS_INST_SUB_DRAIN)
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return true;
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}
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return false;
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}
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