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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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ed4b86828d
It's sufficient to have just one previously set csiphy_formats_sdm845 data. Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Bryan O'Donoghue <bod@kernel.org> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
135 lines
3.2 KiB
C
135 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* camss-csiphy.h
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*
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* Qualcomm MSM Camera Subsystem - CSIPHY Module
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*
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* Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.
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* Copyright (C) 2016-2018 Linaro Ltd.
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*/
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#ifndef QC_MSM_CAMSS_CSIPHY_H
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#define QC_MSM_CAMSS_CSIPHY_H
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <media/media-entity.h>
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#include <media/v4l2-device.h>
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#include <media/v4l2-mediabus.h>
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#include <media/v4l2-subdev.h>
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#define MSM_CSIPHY_PAD_SINK 0
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#define MSM_CSIPHY_PAD_SRC 1
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#define MSM_CSIPHY_PADS_NUM 2
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struct csiphy_lane {
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u8 pos;
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u8 pol;
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};
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/**
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* struct csiphy_lanes_cfg - CSIPHY lanes configuration
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* @num_data: number of data lanes
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* @data: data lanes configuration
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* @clk: clock lane configuration (only for D-PHY)
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*/
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struct csiphy_lanes_cfg {
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int num_data;
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struct csiphy_lane *data;
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struct csiphy_lane clk;
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};
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struct csiphy_csi2_cfg {
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struct csiphy_lanes_cfg lane_cfg;
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};
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struct csiphy_config {
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u8 combo_mode;
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u8 csid_id;
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struct csiphy_csi2_cfg *csi2;
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};
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struct csiphy_format_info {
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u32 code;
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u8 bpp;
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};
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struct csiphy_formats {
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unsigned int nformats;
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const struct csiphy_format_info *formats;
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};
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struct csiphy_device;
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struct csiphy_hw_ops {
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/*
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* csiphy_get_lane_mask - Calculate CSI2 lane mask configuration parameter
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* @lane_cfg - CSI2 lane configuration
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*
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* Return lane mask
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*/
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u8 (*get_lane_mask)(struct csiphy_lanes_cfg *lane_cfg);
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void (*hw_version_read)(struct csiphy_device *csiphy,
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struct device *dev);
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void (*reset)(struct csiphy_device *csiphy);
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void (*lanes_enable)(struct csiphy_device *csiphy,
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struct csiphy_config *cfg,
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s64 link_freq, u8 lane_mask);
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void (*lanes_disable)(struct csiphy_device *csiphy,
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struct csiphy_config *cfg);
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irqreturn_t (*isr)(int irq, void *dev);
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int (*init)(struct csiphy_device *csiphy);
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};
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struct csiphy_subdev_resources {
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u8 id;
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const struct csiphy_hw_ops *hw_ops;
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const struct csiphy_formats *formats;
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};
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struct csiphy_device_regs {
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const struct csiphy_lane_regs *lane_regs;
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int lane_array_size;
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u32 offset;
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};
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struct csiphy_device {
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struct camss *camss;
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u8 id;
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struct v4l2_subdev subdev;
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struct media_pad pads[MSM_CSIPHY_PADS_NUM];
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void __iomem *base;
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void __iomem *base_clk_mux;
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u32 irq;
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char irq_name[30];
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struct camss_clock *clock;
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bool *rate_set;
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int nclocks;
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u32 timer_clk_rate;
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struct regulator_bulk_data *supplies;
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int num_supplies;
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struct csiphy_config cfg;
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struct v4l2_mbus_framefmt fmt[MSM_CSIPHY_PADS_NUM];
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const struct csiphy_subdev_resources *res;
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struct csiphy_device_regs *regs;
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};
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struct camss_subdev_resources;
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int msm_csiphy_subdev_init(struct camss *camss,
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struct csiphy_device *csiphy,
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const struct camss_subdev_resources *res, u8 id);
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int msm_csiphy_register_entity(struct csiphy_device *csiphy,
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struct v4l2_device *v4l2_dev);
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void msm_csiphy_unregister_entity(struct csiphy_device *csiphy);
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extern const struct csiphy_formats csiphy_formats_8x16;
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extern const struct csiphy_formats csiphy_formats_8x96;
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extern const struct csiphy_formats csiphy_formats_sdm845;
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extern const struct csiphy_hw_ops csiphy_ops_2ph_1_0;
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extern const struct csiphy_hw_ops csiphy_ops_3ph_1_0;
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#endif /* QC_MSM_CAMSS_CSIPHY_H */
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