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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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7fc65b78b4
MT8195 and MT8188 share a similar MDP3 macro-block, with minor differences - as in, the latter supports a subset of the number of components supported by the former, but are otherwise handled in the same way. Add driver data for MT8188, reusing the already present MT8195 data where possible. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Fei Shao <fshao@chromium.org> Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
155 lines
3.5 KiB
C
155 lines
3.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Holmes Chiou <holmes.chiou@mediatek.com>
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* Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
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*/
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#ifndef __MTK_IMG_IPI_H__
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#define __MTK_IMG_IPI_H__
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#include <linux/err.h>
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#include "mdp_sm_mt8183.h"
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#include "mdp_sm_mt8195.h"
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#include "mtk-mdp3-type.h"
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/* ISP-MDP generic input information */
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#define IMG_IPI_INIT 1
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#define IMG_IPI_DEINIT 2
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#define IMG_IPI_FRAME 3
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#define IMG_IPI_DEBUG 4
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struct img_timeval {
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u32 tv_sec;
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u32 tv_usec;
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} __packed;
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struct img_addr {
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u64 va; /* Used for Linux OS access */
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u32 pa; /* Used for CM4 access */
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u32 iova; /* Used for IOMMU HW access */
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} __packed;
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struct tuning_addr {
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u64 present;
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u32 pa; /* Used for CM4 access */
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u32 iova; /* Used for IOMMU HW access */
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} __packed;
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struct img_sw_addr {
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u64 va; /* Used for APMCU access */
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u32 pa; /* Used for CM4 access */
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} __packed;
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struct img_plane_format {
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u32 size;
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u32 stride;
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} __packed;
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struct img_pix_format {
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u32 width;
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u32 height;
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u32 colorformat; /* enum mdp_color */
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u32 ycbcr_prof; /* enum mdp_ycbcr_profile */
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struct img_plane_format plane_fmt[IMG_MAX_PLANES];
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} __packed;
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struct img_image_buffer {
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struct img_pix_format format;
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u32 iova[IMG_MAX_PLANES];
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/* enum mdp_buffer_usage, FD or advanced ISP usages */
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u32 usage;
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} __packed;
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#define IMG_SUBPIXEL_SHIFT 20
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#define IMG_CTRL_FLAG_HFLIP BIT(0)
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#define IMG_CTRL_FLAG_DITHER BIT(1)
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#define IMG_CTRL_FLAG_SHARPNESS BIT(4)
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#define IMG_CTRL_FLAG_HDR BIT(5)
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#define IMG_CTRL_FLAG_DRE BIT(6)
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struct img_input {
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struct img_image_buffer buffer;
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u32 flags; /* HDR, DRE, dither */
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} __packed;
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struct img_output {
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struct img_image_buffer buffer;
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struct img_crop crop;
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s32 rotation;
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u32 flags; /* H-flip, sharpness, dither */
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} __packed;
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struct img_ipi_frameparam {
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u32 index;
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u32 frame_no;
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struct img_timeval timestamp;
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u32 type; /* enum mdp_stream_type */
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u32 state;
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u32 num_inputs;
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u32 num_outputs;
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u64 drv_data;
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struct img_input inputs[IMG_MAX_HW_INPUTS];
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struct img_output outputs[IMG_MAX_HW_OUTPUTS];
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struct tuning_addr tuning_data;
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struct img_addr subfrm_data;
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struct img_sw_addr config_data;
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struct img_sw_addr self_data;
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} __packed;
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struct img_sw_buffer {
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u64 handle; /* Used for APMCU access */
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u32 scp_addr; /* Used for CM4 access */
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} __packed;
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struct img_ipi_param {
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u32 usage;
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struct img_sw_buffer frm_param;
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} __packed;
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struct img_frameparam {
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struct list_head list_entry;
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struct img_ipi_frameparam frameparam;
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} __packed;
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/* Platform config indicator */
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#define MT8183 8183
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#define MT8188 8195
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#define MT8195 8195
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#define CFG_CHECK(plat, p_id) ((plat) == (p_id))
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#define _CFG_OFST(plat, cfg, ofst) ((void *)(&((cfg)->config_##plat) + (ofst)))
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#define CFG_OFST(plat, cfg, ofst) \
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(IS_ERR_OR_NULL(cfg) ? NULL : _CFG_OFST(plat, cfg, ofst))
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#define _CFG_ADDR(plat, cfg, mem) (&((cfg)->config_##plat.mem))
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#define CFG_ADDR(plat, cfg, mem) \
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(IS_ERR_OR_NULL(cfg) ? NULL : _CFG_ADDR(plat, cfg, mem))
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#define _CFG_GET(plat, cfg, mem) ((cfg)->config_##plat.mem)
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#define CFG_GET(plat, cfg, mem) \
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(IS_ERR_OR_NULL(cfg) ? 0 : _CFG_GET(plat, cfg, mem))
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#define _CFG_COMP(plat, comp, mem) ((comp)->comp_##plat.mem)
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#define CFG_COMP(plat, comp, mem) \
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(IS_ERR_OR_NULL(comp) ? 0 : _CFG_COMP(plat, comp, mem))
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struct img_config {
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union {
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struct img_config_8183 config_8183;
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struct img_config_8195 config_8195;
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};
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} __packed;
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struct img_compparam {
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union {
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struct img_compparam_8183 comp_8183;
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struct img_compparam_8195 comp_8195;
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};
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} __packed;
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#endif /* __MTK_IMG_IPI_H__ */
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