mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-08-30 21:52:21 +00:00
ced86959d2
The current driver sets the response buffer threshold value to 1 (N+1, 2 DWORDS) in the QUEUE THRESHOLD register. However, the AMD I3C controller only generates interrupts when the response buffer threshold value is set to 0 (1 DWORD). Therefore, a quirk is added to set the response buffer threshold value to 0. Reviewed-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Guruvendra Punugupati <Guruvendra.Punugupati@amd.com> Signed-off-by: Guruvendra Punugupati <Guruvendra.Punugupati@amd.com> Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> Link: https://lore.kernel.org/r/20240829091713.736217-7-Shyam-sundar.S-k@amd.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
45 lines
1.1 KiB
C
45 lines
1.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
|
|
/*
|
|
* I3C HCI Quirks
|
|
*
|
|
* Copyright 2024 Advanced Micro Devices, Inc.
|
|
*
|
|
* Authors: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
|
|
* Guruvendra Punugupati <Guruvendra.Punugupati@amd.com>
|
|
*/
|
|
|
|
#include <linux/i3c/master.h>
|
|
#include "hci.h"
|
|
|
|
/* Timing registers */
|
|
#define HCI_SCL_I3C_OD_TIMING 0x214
|
|
#define HCI_SCL_I3C_PP_TIMING 0x218
|
|
#define HCI_SDA_HOLD_SWITCH_DLY_TIMING 0x230
|
|
|
|
/* Timing values to configure 9MHz frequency */
|
|
#define AMD_SCL_I3C_OD_TIMING 0x00cf00cf
|
|
#define AMD_SCL_I3C_PP_TIMING 0x00160016
|
|
|
|
#define QUEUE_THLD_CTRL 0xD0
|
|
|
|
void amd_set_od_pp_timing(struct i3c_hci *hci)
|
|
{
|
|
u32 data;
|
|
|
|
reg_write(HCI_SCL_I3C_OD_TIMING, AMD_SCL_I3C_OD_TIMING);
|
|
reg_write(HCI_SCL_I3C_PP_TIMING, AMD_SCL_I3C_PP_TIMING);
|
|
data = reg_read(HCI_SDA_HOLD_SWITCH_DLY_TIMING);
|
|
/* Configure maximum TX hold time */
|
|
data |= W0_MASK(18, 16);
|
|
reg_write(HCI_SDA_HOLD_SWITCH_DLY_TIMING, data);
|
|
}
|
|
|
|
void amd_set_resp_buf_thld(struct i3c_hci *hci)
|
|
{
|
|
u32 data;
|
|
|
|
data = reg_read(QUEUE_THLD_CTRL);
|
|
data = data & ~W0_MASK(15, 8);
|
|
reg_write(QUEUE_THLD_CTRL, data);
|
|
}
|