mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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22da60f030
This patch adds support for a new feature, named "Interrupt Delay", allowing driver to set a specific delay time for next interrupt detection. It gives driver a capability to control THC waiting time for the next interrupt, to reduce the likelihood of spurious readings. APIs added: - thc_i2c_set_rx_int_delay(): Set I2C Rx input interrupt delay value - thc_i2c_rx_int_delay_enable(): Enable or disable I2C Rx interrupt delay As this interrupt delay feature is only applicable to RxDMA and must remain disabled during SWDMA operations, it also involves a change in SWDMA code to record the max input size control feature state before SWDMA and restore the state after SWDMA. Signed-off-by: Even Xu <even.xu@intel.com> Tested-by: Chong Han <chong.han@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Jiri Kosina <jkosina@suse.com>
155 lines
5.0 KiB
C
155 lines
5.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2024 Intel Corporation */
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#ifndef _INTEL_THC_DMA_H_
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#define _INTEL_THC_DMA_H_
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#include <linux/bits.h>
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#include <linux/dma-mapping.h>
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#include <linux/sizes.h>
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#include <linux/time64.h>
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#include <linux/types.h>
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#define THC_POINTER_MASK GENMASK(6, 0)
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#define THC_POINTER_WRAPAROUND 0x80
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#define THC_WRAPAROUND_VALUE_ODD 0x10
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#define THC_WRAPAROUND_VALUE_EVEN 0x90
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#define THC_MIN_BYTES_PER_SG_LIST_ENTRY SZ_4K
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#define THC_DEFAULT_RXDMA_POLLING_US_INTERVAL 100
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#define THC_DEFAULT_RXDMA_POLLING_US_TIMEOUT (10 * USEC_PER_MSEC)
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/*
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* THC needs 1KB aligned address, dest_addr is 54 bits, not 64,
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* so don't need to send the lower 10-bits of address.
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*/
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#define THC_ADDRESS_SHIFT 10
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/**
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* THC DMA channels:
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* @THC_RXDMA1: Legacy channel, reserved for raw data reading
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* @THC_RXDMA2: DMA to read HID data from touch device
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* @THC_TXDMA: DMA to write to touch device
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* @THC_SWDMA: SW triggered DMA to write and read from touch device
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*/
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enum thc_dma_channel {
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THC_RXDMA1 = 0,
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THC_RXDMA2 = 1,
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THC_TXDMA = 2,
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THC_SWDMA = 3,
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MAX_THC_DMA_CHANNEL
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};
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/**
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* THC DMA Physical Memory Descriptor (PRD)
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* @dest_addr: Bit[53:0], destination address in system memory
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* @int_on_completion: Bit[63], if set, thc will trigger interrupt to driver
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* @len: Bit[87:64], length of this entry
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* @end_of_prd: Bit[88], if set, this entry is last one of current PRD table
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* @hw_status: Bit[90:89], hardware status bits
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*/
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struct thc_prd_entry {
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u64 dest_addr : 54;
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u64 reserved1 : 9;
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u64 int_on_completion : 1;
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u64 len : 24;
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u64 end_of_prd : 1;
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u64 hw_status : 2;
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u64 reserved2 : 37;
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};
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/*
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* Max OS memory fragmentation will be at a 4KB boundary, thus to address 1MB
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* of virtually contiguous memory 256 PRD entries are required for a single
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* PRD Table. SW writes the number of PRD Entries for each PRD table in the
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* THC_M_PRT_RPRD_CNTRL.PTEC register field. The PRD entry's length must be
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* multiple of 4KB except for the last entry in a PRD table.
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* This is the max possible number of etries supported by HW, in practise we
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* there will be less entries in each prd table(the actual number will be
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* given by scatter-gather list allocation).
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*/
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#define PRD_ENTRIES_NUM 16
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/*
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* Number of PRD tables equals to number of data buffers.
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* The max number of PRD tables supported by the HW is 128,
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* but we allocate only 16.
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*/
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#define PRD_TABLES_NUM 16
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/* THC DMA Physical Memory Descriptor Table */
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struct thc_prd_table {
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struct thc_prd_entry entries[PRD_ENTRIES_NUM];
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};
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#define PRD_TABLE_SIZE sizeof(struct thc_prd_table)
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/**
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* struct thc_dma_configuration - THC DMA configure
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* @dma_channel: DMA channel for current DMA configuration
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* @prd_tbls_dma_handle: DMA buffer handle
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* @dir: Direction of DMA for this config
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* @prd_tbls: PRD tables for current DMA
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* @sgls: Array of pointers to scatter-gather lists
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* @sgls_nent: Actual number of entries per scatter-gather list
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* @prd_tbl_num: Actual number of PRD tables
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* @max_packet_size: Size of the buffer needed for 1 DMA message (1 PRD table)
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* @prd_base_addr_high: High 32bits memory address where stores PRD table
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* @prd_base_addr_low: Low 32bits memory address where stores PRD table
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* @prd_cntrl: PRD control register value
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* @dma_cntrl: DMA control register value
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*/
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struct thc_dma_configuration {
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enum thc_dma_channel dma_channel;
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dma_addr_t prd_tbls_dma_handle;
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enum dma_data_direction dir;
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bool is_enabled;
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struct thc_prd_table *prd_tbls;
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struct scatterlist *sgls[PRD_TABLES_NUM];
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u8 sgls_nent[PRD_TABLES_NUM];
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u8 prd_tbl_num;
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size_t max_packet_size;
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u32 prd_base_addr_high;
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u32 prd_base_addr_low;
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u32 prd_cntrl;
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u32 dma_cntrl;
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};
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/**
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* struct thc_dma_context - THC DMA context
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* @thc_dma_configuration: Array of all THC Channel configures
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* @use_write_interrupts: Indicate TxDMA using interrupt or polling
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* @rx_max_size_en: Temp flag to indicate THC I2C Rx max input size control feature
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* enabled or not, only be used during SWDMA operation.
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* @rx_int_delay_en: Temp flag to indicate THC I2C Rx interrupt delay feature
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* enabled or not, only be used during SWDMA operation.
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*/
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struct thc_dma_context {
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struct thc_dma_configuration dma_config[MAX_THC_DMA_CHANNEL];
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u8 use_write_interrupts;
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bool rx_max_size_en;
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bool rx_int_delay_en;
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};
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struct thc_device;
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int thc_dma_set_max_packet_sizes(struct thc_device *dev,
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size_t mps_read1, size_t mps_read2,
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size_t mps_write, size_t mps_swdma);
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int thc_dma_allocate(struct thc_device *dev);
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int thc_dma_configure(struct thc_device *dev);
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void thc_dma_unconfigure(struct thc_device *dev);
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void thc_dma_release(struct thc_device *dev);
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int thc_rxdma_read(struct thc_device *dev, enum thc_dma_channel dma_channel,
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void *read_buff, size_t *read_len, int *read_finished);
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int thc_swdma_read(struct thc_device *dev, void *write_buff, size_t write_len,
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u32 *prd_tbl_len, void *read_buff, size_t *read_len);
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int thc_dma_write(struct thc_device *dev, void *buffer, size_t buf_len);
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struct thc_dma_context *thc_dma_init(struct thc_device *dev);
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#endif /* _INTEL_THC_DMA_H_ */
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