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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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9f09e31737
i.MX8qxp Display Controller display engine consists of all processing units that operate in a display clock domain. Add minimal feature support with FrameGen and TCon so that the engine can output display timings. The FrameGen driver, TCon driver and display engine driver are components to be aggregated by a master registered in the upcoming DRM driver. Reviewed-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Liu Ying <victor.liu@nxp.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20250414035028.1561475-10-victor.liu@nxp.com
142 lines
3.3 KiB
C
142 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2024 NXP
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*/
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#include <linux/component.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include "dc-drv.h"
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#include "dc-de.h"
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#define TCON_CTRL 0x410
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#define CTRL_RST_VAL 0x01401408
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/* red: MAPBIT 29-20, green: MAPBIT 19-10, blue: MAPBIT 9-0 */
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#define MAPBIT3_0 0x418
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#define MAPBIT7_4 0x41c
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#define MAPBIT11_8 0x420
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#define MAPBIT15_12 0x424
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#define MAPBIT19_16 0x428
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#define MAPBIT23_20 0x42c
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#define MAPBIT27_24 0x430
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#define MAPBIT31_28 0x434
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static const struct dc_subdev_info dc_tc_info[] = {
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{ .reg_start = 0x5618c800, .id = 0, },
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{ .reg_start = 0x5618e400, .id = 1, },
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};
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static const struct regmap_range dc_tc_regmap_ranges[] = {
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regmap_reg_range(TCON_CTRL, TCON_CTRL),
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regmap_reg_range(MAPBIT3_0, MAPBIT31_28),
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};
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static const struct regmap_access_table dc_tc_regmap_access_table = {
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.yes_ranges = dc_tc_regmap_ranges,
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.n_yes_ranges = ARRAY_SIZE(dc_tc_regmap_ranges),
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};
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static const struct regmap_config dc_tc_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.fast_io = true,
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.wr_table = &dc_tc_regmap_access_table,
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.rd_table = &dc_tc_regmap_access_table,
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.max_register = MAPBIT31_28,
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};
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/*
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* The pixels reach TCON are always in 30-bit BGR format.
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* The first bridge always receives pixels in 30-bit RGB format.
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* So, map the format to MEDIA_BUS_FMT_RGB101010_1X30.
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*/
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static const u32 dc_tc_mapbit[] = {
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0x17161514, 0x1b1a1918, 0x0b0a1d1c, 0x0f0e0d0c,
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0x13121110, 0x03020100, 0x07060504, 0x00000908,
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};
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void dc_tc_init(struct dc_tc *tc)
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{
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/* reset TCON_CTRL to POR default so that TCON works in bypass mode */
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regmap_write(tc->reg, TCON_CTRL, CTRL_RST_VAL);
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/* set format */
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regmap_bulk_write(tc->reg, MAPBIT3_0, dc_tc_mapbit,
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ARRAY_SIZE(dc_tc_mapbit));
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}
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static int dc_tc_bind(struct device *dev, struct device *master, void *data)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct dc_drm_device *dc_drm = data;
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struct resource *res;
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void __iomem *base;
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struct dc_tc *tc;
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int id;
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tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL);
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if (!tc)
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return -ENOMEM;
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base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
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if (IS_ERR(base))
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return PTR_ERR(base);
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tc->reg = devm_regmap_init_mmio(dev, base, &dc_tc_regmap_config);
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if (IS_ERR(tc->reg))
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return PTR_ERR(tc->reg);
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id = dc_subdev_get_id(dc_tc_info, ARRAY_SIZE(dc_tc_info), res);
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if (id < 0) {
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dev_err(dev, "failed to get instance number: %d\n", id);
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return id;
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}
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tc->dev = dev;
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dc_drm->tc[id] = tc;
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return 0;
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}
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static const struct component_ops dc_tc_ops = {
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.bind = dc_tc_bind,
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};
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static int dc_tc_probe(struct platform_device *pdev)
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{
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int ret;
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ret = component_add(&pdev->dev, &dc_tc_ops);
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if (ret)
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return dev_err_probe(&pdev->dev, ret,
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"failed to add component\n");
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return 0;
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}
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static void dc_tc_remove(struct platform_device *pdev)
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{
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component_del(&pdev->dev, &dc_tc_ops);
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}
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static const struct of_device_id dc_tc_dt_ids[] = {
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{ .compatible = "fsl,imx8qxp-dc-tcon" },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, dc_tc_dt_ids);
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struct platform_driver dc_tc_driver = {
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.probe = dc_tc_probe,
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.remove = dc_tc_remove,
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.driver = {
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.name = "imx8-dc-tcon",
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.suppress_bind_attrs = true,
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.of_match_table = dc_tc_dt_ids,
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},
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};
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