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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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0e177d5ce0
i.MX8qxp Display Controller pixel engine consists of all processing units that operate in the AXI bus clock domain. Add drivers for ConstFrame, ExtDst, FetchLayer, FetchWarp and LayerBlend units, as well as a pixel engine driver, so that two displays with primary planes can be supported. The pixel engine driver and those unit drivers are components to be aggregated by a master registered in the upcoming DRM driver. Reviewed-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Liu Ying <victor.liu@nxp.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20250414035028.1561475-11-victor.liu@nxp.com
102 lines
2.4 KiB
C
102 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2024 NXP
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*/
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#ifndef __DC_PIXEL_ENGINE_H__
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#define __DC_PIXEL_ENGINE_H__
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/regmap.h>
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#include "dc-de.h"
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#define SHDEN BIT(0)
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#define CLKEN_MASK_SHIFT 24
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#define CLKEN_MASK (0x3 << CLKEN_MASK_SHIFT)
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#define CLKEN(n) ((n) << CLKEN_MASK_SHIFT)
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#define DC_DISP_FU_CNT 2
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#define DC_LB_CNT 4
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enum dc_link_id {
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LINK_ID_NONE = 0x00,
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LINK_ID_CONSTFRAME0 = 0x0c,
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LINK_ID_CONSTFRAME4 = 0x0e,
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LINK_ID_CONSTFRAME1 = 0x10,
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LINK_ID_CONSTFRAME5 = 0x12,
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LINK_ID_FETCHWARP2 = 0x14,
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LINK_ID_FETCHLAYER0 = 0x1a,
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LINK_ID_LAYERBLEND0 = 0x21,
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LINK_ID_LAYERBLEND1 = 0x22,
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LINK_ID_LAYERBLEND2 = 0x23,
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LINK_ID_LAYERBLEND3 = 0x24,
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};
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enum dc_lb_mode {
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LB_NEUTRAL, /* Output is same as primary input. */
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LB_BLEND,
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};
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enum dc_pec_clken {
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CLKEN_DISABLE,
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CLKEN_AUTOMATIC,
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};
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struct dc_cf {
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struct regmap *reg_cfg;
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enum dc_link_id link;
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};
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struct dc_ed {
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struct device *dev;
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struct regmap *reg_pec;
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struct regmap *reg_cfg;
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int irq_shdload;
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};
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struct dc_lb {
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struct device *dev;
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struct regmap *reg_pec;
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struct regmap *reg_cfg;
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int id;
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enum dc_link_id link;
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};
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struct dc_pe {
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struct device *dev;
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struct clk *clk_axi;
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struct dc_cf *cf_safe[DC_DISPLAYS];
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struct dc_cf *cf_cont[DC_DISPLAYS];
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struct dc_ed *ed_safe[DC_DISPLAYS];
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struct dc_ed *ed_cont[DC_DISPLAYS];
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struct dc_fu *fu_disp[DC_DISP_FU_CNT];
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struct dc_lb *lb[DC_LB_CNT];
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};
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/* Constant Frame Unit */
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enum dc_link_id dc_cf_get_link_id(struct dc_cf *cf);
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void dc_cf_framedimensions(struct dc_cf *cf, unsigned int w, unsigned int h);
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void dc_cf_constantcolor_black(struct dc_cf *cf);
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void dc_cf_constantcolor_blue(struct dc_cf *cf);
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void dc_cf_init(struct dc_cf *cf);
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/* External Destination Unit */
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void dc_ed_pec_src_sel(struct dc_ed *ed, enum dc_link_id src);
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void dc_ed_pec_sync_trigger(struct dc_ed *ed);
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void dc_ed_init(struct dc_ed *ed);
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/* Layer Blend Unit */
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enum dc_link_id dc_lb_get_link_id(struct dc_lb *lb);
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void dc_lb_pec_dynamic_prim_sel(struct dc_lb *lb, enum dc_link_id prim);
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void dc_lb_pec_dynamic_sec_sel(struct dc_lb *lb, enum dc_link_id sec);
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void dc_lb_pec_clken(struct dc_lb *lb, enum dc_pec_clken clken);
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void dc_lb_mode(struct dc_lb *lb, enum dc_lb_mode mode);
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void dc_lb_position(struct dc_lb *lb, int x, int y);
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int dc_lb_get_id(struct dc_lb *lb);
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void dc_lb_init(struct dc_lb *lb);
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#endif /* __DC_PIXEL_ENGINE_H__ */
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