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711a3b8783
i.MX8qxp Display Controller(DC) is comprised of three main components that include a blit engine for 2D graphics accelerations, display controller for display output processing, as well as a command sequencer. Add kernel mode setting support for the display controller part with two CRTCs and two primary planes(backed by FetchLayer and FetchWarp respectively). The registers of the display controller are accessed without command sequencer involved, instead just by using CPU. The command sequencer is supposed to be used by the blit engine. Reviewed-by: Maxime Ripard <mripard@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Liu Ying <victor.liu@nxp.com> Link: https://lore.kernel.org/r/20250414035028.1561475-13-victor.liu@nxp.com
14 lines
408 B
Plaintext
14 lines
408 B
Plaintext
config DRM_IMX8_DC
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tristate "Freescale i.MX8 Display Controller Graphics"
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depends on DRM && COMMON_CLK && OF && (ARCH_MXC || COMPILE_TEST)
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select DRM_CLIENT_SELECTION
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select DRM_GEM_DMA_HELPER
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select DRM_KMS_HELPER
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select DRM_DISPLAY_HELPER
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select DRM_BRIDGE_CONNECTOR
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select GENERIC_IRQ_CHIP
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select REGMAP
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select REGMAP_MMIO
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help
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enable Freescale i.MX8 Display Controller(DC) graphics support
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