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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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171f378d2a
Newer PowerVR GPUs (such as the BXS-4-64 MC1) use a RISC-V firmware processor instead of the previous MIPS or META. The current version of this patch depends on a patch[1] which exists in drm-misc-fixes, but has not yet made it back to drm-misc-next (the target of this patch). That patch adds the function pvr_vm_unmap_obj() which is used here. [1]: https://lore.kernel.org/r/20250226-hold-drm_gem_gpuva-lock-for-unmap-v2-1-3fdacded227f@imgtec.com Signed-off-by: Sarah Walker <sarah.walker@imgtec.com> Reviewed-by: Frank Binns <frank.binns@imgtec.com> Link: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-14-eda620c5865f@imgtec.com Signed-off-by: Matt Coster <matt.coster@imgtec.com>
42 lines
1.2 KiB
C
42 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
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/* Copyright (c) 2024 Imagination Technologies Ltd. */
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#ifndef PVR_ROGUE_RISCV_H
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#define PVR_ROGUE_RISCV_H
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#include "pvr_rogue_cr_defs.h"
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#include <linux/bitops.h>
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#include <linux/sizes.h>
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#include <linux/types.h>
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#define ROGUE_RISCVFW_REGION_SIZE SZ_256M
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#define ROGUE_RISCVFW_REGION_SHIFT __ffs(ROGUE_RISCVFW_REGION_SIZE)
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enum rogue_riscvfw_region {
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ROGUE_RISCV_REGION__RESERVED_0 = 0,
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ROGUE_RISCV_REGION__RESERVED_1,
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ROGUE_RISCV_REGION_SOCIF,
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ROGUE_RISCV_REGION__RESERVED_3,
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ROGUE_RISCV_REGION__RESERVED_4,
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ROGUE_RISCV_REGION_BOOTLDR_DATA,
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ROGUE_RISCV_REGION_SHARED_CACHED_DATA,
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ROGUE_RISCV_REGION__RESERVED_7,
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ROGUE_RISCV_REGION_COREMEM,
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ROGUE_RISCV_REGION__RESERVED_9,
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ROGUE_RISCV_REGION__RESERVED_A,
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ROGUE_RISCV_REGION__RESERVED_B,
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ROGUE_RISCV_REGION_BOOTLDR_CODE,
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ROGUE_RISCV_REGION_SHARED_UNCACHED_DATA,
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ROGUE_RISCV_REGION__RESERVED_E,
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ROGUE_RISCV_REGION__RESERVED_F,
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ROGUE_RISCV_REGION__COUNT,
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};
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#define ROGUE_RISCVFW_REGION_BASE(r) ((u32)(ROGUE_RISCV_REGION_##r) << ROGUE_RISCVFW_REGION_SHIFT)
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#define ROGUE_RISCVFW_REGION_REMAP_CR(r) \
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(ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0 + (u32)(ROGUE_RISCV_REGION_##r) * 8U)
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#endif /* PVR_ROGUE_RISCV_H */
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