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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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00efddc608
Extract the VGACNTR register definitions into their own header file, to declutter i915_reg.h a bit. v2: Group the register offst definitions together (Jani) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250417114454.12836-4-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
37 lines
1.5 KiB
C
37 lines
1.5 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2025 Intel Corporation
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*/
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#ifndef __INTEL_VGA_REGS_H__
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#define __INTEL_VGA_REGS_H__
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#include "intel_display_reg_defs.h"
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#define VGACNTRL _MMIO(0x71400)
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#define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400)
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#define CPU_VGACNTRL _MMIO(0x41000)
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#define VGA_DISP_DISABLE REG_BIT(31)
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#define VGA_2X_MODE REG_BIT(30) /* pre-ilk */
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#define VGA_PIPE_SEL_MASK REG_BIT(29) /* pre-ivb */
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#define VGA_PIPE_SEL(pipe) REG_FIELD_PREP(VGA_PIPE_SEL_MASK, (pipe))
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#define VGA_PIPE_SEL_MASK_CHV REG_GENMASK(29, 28) /* chv */
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#define VGA_PIPE_SEL_CHV(pipe) REG_FIELD_PREP(VGA_PIPE_SEL_MASK_CHV, (pipe))
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#define VGA_BORDER_ENABLE REG_BIT(26)
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#define VGA_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
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#define VGA_CENTERING_ENABLE_MASK REG_GENMASK(25, 24) /* pre-ilk */
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#define VGA_PALETTE_READ_SEL REG_BIT(23) /* pre-ivb */
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#define VGA_PALETTE_A_WRITE_DISABLE REG_BIT(22) /* pre-ivb */
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#define VGA_PALETTE_B_WRITE_DISABLE REG_BIT(21) /* pre-ivb */
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#define VGA_LEGACY_8BIT_PALETTE_ENABLE REG_BIT(20)
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#define VGA_PALETTE_BYPASS REG_BIT(19)
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#define VGA_NINE_DOT_DISABLE REG_BIT(18)
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#define VGA_PALETTE_READ_SEL_HI_CHV REG_BIT(15) /* chv */
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#define VGA_PALETTE_C_WRITE_DISABLE_CHV REG_BIT(14) /* chv */
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#define VGA_ACTIVE_THROTTLING_MASK REG_GENMASK(15, 12) /* ilk+ */
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#define VGA_BLANK_THROTTLING_MASK REG_GENMASK(11, 8) /* ilk+ */
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#define VGA_BLINK_DUTY_CYCLE_MASK REG_GENMASK(7, 6)
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#define VGA_VSYNC_BLINK_RATE_MASK REG_GENMASK(5, 0)
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#endif /* __INTEL_VGA_REGS_H__ */
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