Aric Cyr 024771f3fb drm/amd/display: Optimize cursor position updates ... [why] Updating the cursor enablement register can be a slow operation and accumulates when high polling rate cursors cause frequent updates asynchronously to the cursor position. [how] Since the cursor enable bit is cached there is no need to update the enablement register if there is no change to it. This removes the read-modify-write from the cursor position programming path in HUBP and DPP, leaving only the register writes. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by: Sung Lee <sung.lee@amd.com> Signed-off-by: Aric Cyr <Aric.Cyr@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2025-01-24 09:56:28 -05:00
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dcn10_dpp_cm.c	drm/amd/display: Remove unnecessary call to REG_SEQ_SUBMIT|WAIT_DONE	2024-08-13 12:12:51 -04:00
dcn10_dpp_dscl.c
dcn10_dpp.c	drm/amd/display: Optimize cursor position updates	2025-01-24 09:56:28 -05:00
dcn10_dpp.h