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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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9750ad5aee
Add an API to set the max possible xgmi speed/width. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
130 lines
4.4 KiB
C
130 lines
4.4 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __AMDGPU_XGMI_H__
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#define __AMDGPU_XGMI_H__
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#include <drm/task_barrier.h>
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#include "amdgpu_ras.h"
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struct amdgpu_hive_info {
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struct kobject kobj;
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uint64_t hive_id;
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struct list_head device_list;
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struct list_head node;
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atomic_t number_devices;
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struct mutex hive_lock;
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int hi_req_count;
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struct amdgpu_device *hi_req_gpu;
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struct task_barrier tb;
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enum {
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AMDGPU_XGMI_PSTATE_MIN,
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AMDGPU_XGMI_PSTATE_MAX_VEGA20,
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AMDGPU_XGMI_PSTATE_UNKNOWN
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} pstate;
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struct amdgpu_reset_domain *reset_domain;
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atomic_t ras_recovery;
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struct ras_event_manager event_mgr;
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struct work_struct reset_on_init_work;
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atomic_t requested_nps_mode;
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};
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struct amdgpu_pcs_ras_field {
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const char *err_name;
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uint32_t pcs_err_mask;
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uint32_t pcs_err_shift;
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};
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/**
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* Bandwidth range reporting comes in two modes.
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*
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* PER_LINK - range for any xgmi link
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* PER_PEER - range of max of single xgmi link to max of multiple links based on source peer
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*/
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enum amdgpu_xgmi_bw_mode {
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AMDGPU_XGMI_BW_MODE_PER_LINK = 0,
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AMDGPU_XGMI_BW_MODE_PER_PEER
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};
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enum amdgpu_xgmi_bw_unit {
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AMDGPU_XGMI_BW_UNIT_GBYTES = 0,
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AMDGPU_XGMI_BW_UNIT_MBYTES
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};
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struct amdgpu_xgmi_ras {
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struct amdgpu_ras_block_object ras_block;
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};
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extern struct amdgpu_xgmi_ras xgmi_ras;
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struct amdgpu_xgmi {
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/* from psp */
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u64 node_id;
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u64 hive_id;
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/* fixed per family */
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u64 node_segment_size;
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/* physical node (0-3) */
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unsigned physical_node_id;
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/* number of nodes (0-4) */
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unsigned num_physical_nodes;
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/* gpu list in the same hive */
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struct list_head head;
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bool supported;
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struct ras_common_if *ras_if;
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bool connected_to_cpu;
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struct amdgpu_xgmi_ras *ras;
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uint16_t max_speed;
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uint8_t max_width;
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};
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struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev);
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void amdgpu_put_xgmi_hive(struct amdgpu_hive_info *hive);
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int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct amdgpu_device *adev);
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int amdgpu_xgmi_add_device(struct amdgpu_device *adev);
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int amdgpu_xgmi_remove_device(struct amdgpu_device *adev);
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int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate);
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int amdgpu_xgmi_get_hops_count(struct amdgpu_device *adev, struct amdgpu_device *peer_adev);
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int amdgpu_xgmi_get_bandwidth(struct amdgpu_device *adev, struct amdgpu_device *peer_adev,
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enum amdgpu_xgmi_bw_mode bw_mode, enum amdgpu_xgmi_bw_unit bw_unit,
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uint32_t *min_bw, uint32_t *max_bw);
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bool amdgpu_xgmi_get_is_sharing_enabled(struct amdgpu_device *adev,
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struct amdgpu_device *peer_adev);
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uint64_t amdgpu_xgmi_get_relative_phy_addr(struct amdgpu_device *adev,
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uint64_t addr);
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bool amdgpu_xgmi_same_hive(struct amdgpu_device *adev,
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struct amdgpu_device *bo_adev);
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int amdgpu_xgmi_ras_sw_init(struct amdgpu_device *adev);
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int amdgpu_xgmi_reset_on_init(struct amdgpu_device *adev);
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int amdgpu_xgmi_request_nps_change(struct amdgpu_device *adev,
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struct amdgpu_hive_info *hive,
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int req_nps_mode);
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int amdgpu_get_xgmi_link_status(struct amdgpu_device *adev,
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int global_link_num);
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int amdgpu_xgmi_get_ext_link(struct amdgpu_device *adev, int link_num);
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void amdgpu_xgmi_early_init(struct amdgpu_device *adev);
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uint32_t amdgpu_xgmi_get_max_bandwidth(struct amdgpu_device *adev);
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void amgpu_xgmi_set_max_speed_width(struct amdgpu_device *adev,
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uint16_t max_speed, uint8_t max_width);
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#endif
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