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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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0c3c2e334c
Add a parameter to amdgpu_sdma_reset_engine() to let the caller handle the kernel rings. This allows the kernel rings to back up their unprocessed state if the reset comes in via the drm scheduler rather than KFD. Reviewed-by: Jesse Zhang <Jesse.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
205 lines
6.7 KiB
C
205 lines
6.7 KiB
C
/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_SDMA_H__
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#define __AMDGPU_SDMA_H__
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#include "amdgpu_ras.h"
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/* max number of IP instances */
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#define AMDGPU_MAX_SDMA_INSTANCES 16
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enum amdgpu_sdma_irq {
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AMDGPU_SDMA_IRQ_INSTANCE0 = 0,
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AMDGPU_SDMA_IRQ_INSTANCE1,
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AMDGPU_SDMA_IRQ_INSTANCE2,
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AMDGPU_SDMA_IRQ_INSTANCE3,
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AMDGPU_SDMA_IRQ_INSTANCE4,
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AMDGPU_SDMA_IRQ_INSTANCE5,
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AMDGPU_SDMA_IRQ_INSTANCE6,
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AMDGPU_SDMA_IRQ_INSTANCE7,
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AMDGPU_SDMA_IRQ_INSTANCE8,
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AMDGPU_SDMA_IRQ_INSTANCE9,
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AMDGPU_SDMA_IRQ_INSTANCE10,
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AMDGPU_SDMA_IRQ_INSTANCE11,
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AMDGPU_SDMA_IRQ_INSTANCE12,
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AMDGPU_SDMA_IRQ_INSTANCE13,
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AMDGPU_SDMA_IRQ_INSTANCE14,
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AMDGPU_SDMA_IRQ_INSTANCE15,
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AMDGPU_SDMA_IRQ_LAST
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};
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#define NUM_SDMA(x) hweight32(x)
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struct amdgpu_sdma_funcs {
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int (*stop_kernel_queue)(struct amdgpu_ring *ring);
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int (*start_kernel_queue)(struct amdgpu_ring *ring);
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int (*soft_reset_kernel_queue)(struct amdgpu_device *adev, u32 instance_id);
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};
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struct amdgpu_sdma_instance {
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/* SDMA firmware */
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const struct firmware *fw;
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uint32_t fw_version;
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uint32_t feature_version;
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struct amdgpu_ring ring;
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struct amdgpu_ring page;
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bool burst_nop;
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uint32_t aid_id;
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struct amdgpu_bo *sdma_fw_obj;
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uint64_t sdma_fw_gpu_addr;
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uint32_t *sdma_fw_ptr;
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struct mutex engine_reset_mutex;
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/* track guilty state of GFX and PAGE queues */
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bool gfx_guilty;
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bool page_guilty;
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const struct amdgpu_sdma_funcs *funcs;
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};
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enum amdgpu_sdma_ras_memory_id {
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AMDGPU_SDMA_MBANK_DATA_BUF0 = 1,
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AMDGPU_SDMA_MBANK_DATA_BUF1 = 2,
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AMDGPU_SDMA_MBANK_DATA_BUF2 = 3,
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AMDGPU_SDMA_MBANK_DATA_BUF3 = 4,
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AMDGPU_SDMA_MBANK_DATA_BUF4 = 5,
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AMDGPU_SDMA_MBANK_DATA_BUF5 = 6,
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AMDGPU_SDMA_MBANK_DATA_BUF6 = 7,
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AMDGPU_SDMA_MBANK_DATA_BUF7 = 8,
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AMDGPU_SDMA_MBANK_DATA_BUF8 = 9,
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AMDGPU_SDMA_MBANK_DATA_BUF9 = 10,
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AMDGPU_SDMA_MBANK_DATA_BUF10 = 11,
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AMDGPU_SDMA_MBANK_DATA_BUF11 = 12,
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AMDGPU_SDMA_MBANK_DATA_BUF12 = 13,
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AMDGPU_SDMA_MBANK_DATA_BUF13 = 14,
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AMDGPU_SDMA_MBANK_DATA_BUF14 = 15,
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AMDGPU_SDMA_MBANK_DATA_BUF15 = 16,
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AMDGPU_SDMA_UCODE_BUF = 17,
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AMDGPU_SDMA_RB_CMD_BUF = 18,
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AMDGPU_SDMA_IB_CMD_BUF = 19,
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AMDGPU_SDMA_UTCL1_RD_FIFO = 20,
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AMDGPU_SDMA_UTCL1_RDBST_FIFO = 21,
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AMDGPU_SDMA_UTCL1_WR_FIFO = 22,
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AMDGPU_SDMA_DATA_LUT_FIFO = 23,
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AMDGPU_SDMA_SPLIT_DAT_BUF = 24,
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AMDGPU_SDMA_MEMORY_BLOCK_LAST,
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};
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struct amdgpu_sdma_ras {
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struct amdgpu_ras_block_object ras_block;
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};
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struct amdgpu_sdma {
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struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
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struct amdgpu_irq_src trap_irq;
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struct amdgpu_irq_src illegal_inst_irq;
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struct amdgpu_irq_src fence_irq;
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struct amdgpu_irq_src ecc_irq;
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struct amdgpu_irq_src vm_hole_irq;
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struct amdgpu_irq_src doorbell_invalid_irq;
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struct amdgpu_irq_src pool_timeout_irq;
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struct amdgpu_irq_src srbm_write_irq;
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struct amdgpu_irq_src ctxt_empty_irq;
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int num_instances;
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uint32_t sdma_mask;
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int num_inst_per_aid;
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uint32_t srbm_soft_reset;
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bool has_page_queue;
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struct ras_common_if *ras_if;
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struct amdgpu_sdma_ras *ras;
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uint32_t *ip_dump;
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uint32_t supported_reset;
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struct list_head reset_callback_list;
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bool no_user_submission;
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bool disable_uq;
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};
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/*
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* Provided by hw blocks that can move/clear data. e.g., gfx or sdma
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* But currently, we use sdma to move data.
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*/
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struct amdgpu_buffer_funcs {
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/* maximum bytes in a single operation */
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uint32_t copy_max_bytes;
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/* number of dw to reserve per operation */
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unsigned copy_num_dw;
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/* used for buffer migration */
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void (*emit_copy_buffer)(struct amdgpu_ib *ib,
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/* src addr in bytes */
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uint64_t src_offset,
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/* dst addr in bytes */
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uint64_t dst_offset,
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/* number of byte to transfer */
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uint32_t byte_count,
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uint32_t copy_flags);
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/* maximum bytes in a single operation */
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uint32_t fill_max_bytes;
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/* number of dw to reserve per operation */
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unsigned fill_num_dw;
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/* used for buffer clearing */
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void (*emit_fill_buffer)(struct amdgpu_ib *ib,
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/* value to write to memory */
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uint32_t src_data,
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/* dst addr in bytes */
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uint64_t dst_offset,
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/* number of byte to fill */
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uint32_t byte_count);
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};
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int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id,
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bool caller_handles_kernel_queues);
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#define amdgpu_emit_copy_buffer(adev, ib, s, d, b, t) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b), (t))
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#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
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struct amdgpu_sdma_instance *
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amdgpu_sdma_get_instance_from_ring(struct amdgpu_ring *ring);
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int amdgpu_sdma_get_index_from_ring(struct amdgpu_ring *ring, uint32_t *index);
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uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring, unsigned vmid);
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int amdgpu_sdma_ras_late_init(struct amdgpu_device *adev,
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struct ras_common_if *ras_block);
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int amdgpu_sdma_process_ras_data_cb(struct amdgpu_device *adev,
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void *err_data,
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struct amdgpu_iv_entry *entry);
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int amdgpu_sdma_process_ecc_irq(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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struct amdgpu_iv_entry *entry);
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int amdgpu_sdma_init_microcode(struct amdgpu_device *adev, u32 instance,
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bool duplicate);
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void amdgpu_sdma_destroy_inst_ctx(struct amdgpu_device *adev,
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bool duplicate);
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int amdgpu_sdma_ras_sw_init(struct amdgpu_device *adev);
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void amdgpu_debugfs_sdma_sched_mask_init(struct amdgpu_device *adev);
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int amdgpu_sdma_sysfs_reset_mask_init(struct amdgpu_device *adev);
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void amdgpu_sdma_sysfs_reset_mask_fini(struct amdgpu_device *adev);
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bool amdgpu_sdma_is_shared_inv_eng(struct amdgpu_device *adev, struct amdgpu_ring *ring);
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struct amdgpu_ring *amdgpu_sdma_get_shared_ring(struct amdgpu_device *adev,
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struct amdgpu_ring *ring);
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#endif
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