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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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7212b58d6d
Both Intel and AMD CPUs support 5-level paging, which is expected to become more widely adopted in the future. All major x86 Linux distributions have the feature enabled. Remove CONFIG_X86_5LEVEL and related #ifdeffery for it to make it more readable. Suggested-by: Borislav Petkov <bp@alien8.de> Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Borislav Petkov (AMD) <bp@alien8.de> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Link: https://lore.kernel.org/r/20250516123306.3812286-4-kirill.shutemov@linux.intel.com
96 lines
2.8 KiB
C
96 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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#include <linux/efi.h>
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#include <asm/boot.h>
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#include <asm/desc.h>
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#include <asm/efi.h>
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#include "efistub.h"
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#include "x86-stub.h"
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bool efi_no5lvl;
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static void (*la57_toggle)(void *cr3);
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static const struct desc_struct gdt[] = {
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[GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(DESC_CODE32, 0, 0xfffff),
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[GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(DESC_CODE64, 0, 0xfffff),
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};
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/*
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* Enabling (or disabling) 5 level paging is tricky, because it can only be
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* done from 32-bit mode with paging disabled. This means not only that the
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* code itself must be running from 32-bit addressable physical memory, but
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* also that the root page table must be 32-bit addressable, as programming
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* a 64-bit value into CR3 when running in 32-bit mode is not supported.
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*/
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efi_status_t efi_setup_5level_paging(void)
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{
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u8 tmpl_size = (u8 *)&trampoline_ljmp_imm_offset - (u8 *)&trampoline_32bit_src;
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efi_status_t status;
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u8 *la57_code;
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if (!efi_is_64bit())
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return EFI_SUCCESS;
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/* check for 5 level paging support */
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if (native_cpuid_eax(0) < 7 ||
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!(native_cpuid_ecx(7) & (1 << (X86_FEATURE_LA57 & 31))))
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return EFI_SUCCESS;
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/* allocate some 32-bit addressable memory for code and a page table */
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status = efi_allocate_pages(2 * PAGE_SIZE, (unsigned long *)&la57_code,
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U32_MAX);
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if (status != EFI_SUCCESS)
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return status;
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la57_toggle = memcpy(la57_code, trampoline_32bit_src, tmpl_size);
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memset(la57_code + tmpl_size, 0x90, PAGE_SIZE - tmpl_size);
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/*
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* To avoid the need to allocate a 32-bit addressable stack, the
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* trampoline uses a LJMP instruction to switch back to long mode.
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* LJMP takes an absolute destination address, which needs to be
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* fixed up at runtime.
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*/
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*(u32 *)&la57_code[trampoline_ljmp_imm_offset] += (unsigned long)la57_code;
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efi_adjust_memory_range_protection((unsigned long)la57_toggle, PAGE_SIZE);
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return EFI_SUCCESS;
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}
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void efi_5level_switch(void)
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{
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bool want_la57 = !efi_no5lvl;
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bool have_la57 = native_read_cr4() & X86_CR4_LA57;
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bool need_toggle = want_la57 ^ have_la57;
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u64 *pgt = (void *)la57_toggle + PAGE_SIZE;
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u64 *cr3 = (u64 *)__native_read_cr3();
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u64 *new_cr3;
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if (!la57_toggle || !need_toggle)
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return;
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if (!have_la57) {
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/*
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* 5 level paging will be enabled, so a root level page needs
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* to be allocated from the 32-bit addressable physical region,
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* with its first entry referring to the existing hierarchy.
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*/
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new_cr3 = memset(pgt, 0, PAGE_SIZE);
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new_cr3[0] = (u64)cr3 | _PAGE_TABLE_NOENC;
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} else {
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/* take the new root table pointer from the current entry #0 */
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new_cr3 = (u64 *)(cr3[0] & PAGE_MASK);
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/* copy the new root table if it is not 32-bit addressable */
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if ((u64)new_cr3 > U32_MAX)
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new_cr3 = memcpy(pgt, new_cr3, PAGE_SIZE);
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}
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native_load_gdt(&(struct desc_ptr){ sizeof(gdt) - 1, (u64)gdt });
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la57_toggle(new_cr3);
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}
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