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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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b7dbde2b82
Implement phase offset monitor feature to allow a user to monitor phase offsets across all available inputs. The device firmware periodically performs phase offsets measurements for all available DPLL channels and input references. The driver can ask the firmware to fill appropriate latch registers with measured values. There are 2 sets of latch registers for phase offsets reporting: 1) DPLL-to-connected-ref: up to 5 registers that contain values for phase offset between particular DPLL channel and its connected input reference. 2) selected-DPLL-to-ref: 10 registers that contain values for phase offsets between selected DPLL channel and all available input references. Both are filled with single read request so the driver can read DPLL-to-connected-ref phase offset for all DPLL channels at once. This was implemented in the previous patch. To read selected-DPLL-to-ref registers for all DPLLs a separate read request has to be sent to device firmware for each DPLL channel. To implement phase offset monitor feature: * Extend zl3073x_ref_phase_offsets_update() to select given DPLL channel in phase offset read request. The caller can set channel==-1 if it will not read Type2 registers. * Use this extended function to update phase offset latch registers during zl3073x_dpll_changes_check() call if phase monitor is enabled * Extend zl3073x_dpll_pin_phase_offset_check() to check phase offset changes for all available input references * Extend zl3073x_dpll_input_pin_phase_offset_get() to report phase offset values for all available input references * Implement phase offset monitor callbacks to enable/disable this feature Reviewed-by: Jiri Pirko <jiri@nvidia.com> Tested-by: Prathosh Satish <prathosh.satish@microchip.com> Co-developed-by: Prathosh Satish <Prathosh.Satish@microchip.com> Signed-off-by: Prathosh Satish <Prathosh.Satish@microchip.com> Signed-off-by: Ivan Vecera <ivecera@redhat.com> Link: https://patch.msgid.link/20250715144633.149156-4-ivecera@redhat.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
47 lines
1.3 KiB
C
47 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _ZL3073X_DPLL_H
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#define _ZL3073X_DPLL_H
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#include <linux/dpll.h>
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#include <linux/list.h>
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#include "core.h"
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/**
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* struct zl3073x_dpll - ZL3073x DPLL sub-device structure
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* @list: this DPLL list entry
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* @dev: pointer to multi-function parent device
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* @id: DPLL index
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* @refsel_mode: reference selection mode
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* @forced_ref: selected reference in forced reference lock mode
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* @check_count: periodic check counter
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* @phase_monitor: is phase offset monitor enabled
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* @dpll_dev: pointer to registered DPLL device
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* @lock_status: last saved DPLL lock status
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* @pins: list of pins
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*/
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struct zl3073x_dpll {
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struct list_head list;
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struct zl3073x_dev *dev;
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u8 id;
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u8 refsel_mode;
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u8 forced_ref;
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u8 check_count;
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bool phase_monitor;
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struct dpll_device *dpll_dev;
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enum dpll_lock_status lock_status;
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struct list_head pins;
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};
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struct zl3073x_dpll *zl3073x_dpll_alloc(struct zl3073x_dev *zldev, u8 ch);
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void zl3073x_dpll_free(struct zl3073x_dpll *zldpll);
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int zl3073x_dpll_register(struct zl3073x_dpll *zldpll);
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void zl3073x_dpll_unregister(struct zl3073x_dpll *zldpll);
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int zl3073x_dpll_init_fine_phase_adjust(struct zl3073x_dev *zldev);
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void zl3073x_dpll_changes_check(struct zl3073x_dpll *zldpll);
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#endif /* _ZL3073X_DPLL_H */
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