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7cae1e2b55
Add the PLL clocks of the main CCU of the Allwinner A523 and T527 SoCs. The clocks were modelled after the A523 and T527 manual, and double checked by writing all 1's into the respective register, to spot all implemented bits. The PLL and mod clocks for the two CPU clusters and the DSU are part of a separate CCU, also most audio clocks are collected in a DSP CCU, so both of these clock groups are missing from this driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20250307002628.10684-6-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
15 lines
294 B
C
15 lines
294 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright 2024 Arm Ltd.
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*/
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#ifndef _CCU_SUN55I_A523_H
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#define _CCU_SUN55I_A523_H
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#include <dt-bindings/clock/sun55i-a523-ccu.h>
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#include <dt-bindings/reset/sun55i-a523-ccu.h>
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#define CLK_NUMBER (CLK_FANOUT2 + 1)
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#endif /* _CCU_SUN55I_A523_H */
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