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1b72c59db0
The clock tree of K1 SoC contains three main types of clock hardware (PLL/DDN/MIX) and has control registers split into several multifunction devices: APBS (PLLs), MPMU, APBC and APMU. All register operations are done through regmap to ensure atomicity between concurrent operations of clock driver and reset, power-domain driver that will be introduced in the future. Signed-off-by: Haylen Chu <heylenay@4d2.org> Reviewed-by: Alex Elder <elder@riscstar.com> Reviewed-by: Inochi Amaoto <inochiama@outlook.com> Reviewed-by: Yixun Lan <dlan@gentoo.org> Link: https://lore.kernel.org/r/20250416135406.16284-4-heylenay@4d2.org Signed-off-by: Yixun Lan <dlan@gentoo.org>
6 lines
168 B
Makefile
6 lines
168 B
Makefile
# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_SPACEMIT_K1_CCU) = spacemit-ccu-k1.o
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spacemit-ccu-k1-y = ccu_pll.o ccu_mix.o ccu_ddn.o
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spacemit-ccu-k1-y += ccu-k1.o
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