mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-08-31 22:23:05 +00:00
f00b45db02
After commit 0edb555a65 ("platform: Make platform_driver::remove()
return void") .remove() is (again) the right callback to implement for
platform drivers.
Convert all clk drivers to use .remove(), with the eventual goal to drop
struct platform_driver::remove_new(). As .remove() and .remove_new() have
the same prototypes, conversion is done by just changing the structure
member name in the driver initializer.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
Link: https://lore.kernel.org/r/20240909144026.870565-2-u.kleine-koenig@baylibre.com
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> # renesas
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
83 lines
2.1 KiB
C
83 lines
2.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2023 Daniel Golle <daniel@makrotopia.org>
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*/
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mediatek,mt7988-clk.h>
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/* Register to control USXGMII XFI PLL analog */
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#define XFI_PLL_ANA_GLB8 0x108
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#define RG_XFI_PLL_ANA_SWWA 0x02283248
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static const struct mtk_gate_regs xfipll_cg_regs = {
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.set_ofs = 0x8,
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.clr_ofs = 0x8,
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.sta_ofs = 0x8,
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};
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#define GATE_XFIPLL(_id, _name, _parent, _shift) \
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{ \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &xfipll_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_no_setclr_inv, \
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}
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static const struct mtk_fixed_factor xfipll_divs[] = {
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FACTOR(CLK_XFIPLL_PLL, "xfipll_pll", "top_xtal", 125, 32),
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};
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static const struct mtk_gate xfipll_clks[] = {
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GATE_XFIPLL(CLK_XFIPLL_PLL_EN, "xfipll_pll_en", "xfipll_pll", 31),
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};
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static const struct mtk_clk_desc xfipll_desc = {
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.clks = xfipll_clks,
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.num_clks = ARRAY_SIZE(xfipll_clks),
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.factor_clks = xfipll_divs,
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.num_factor_clks = ARRAY_SIZE(xfipll_divs),
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};
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static int clk_mt7988_xfipll_probe(struct platform_device *pdev)
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{
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struct device_node *node = pdev->dev.of_node;
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void __iomem *base = of_iomap(node, 0);
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if (!base)
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return -ENOMEM;
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/* Apply software workaround for USXGMII PLL TCL issue */
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writel(RG_XFI_PLL_ANA_SWWA, base + XFI_PLL_ANA_GLB8);
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iounmap(base);
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return mtk_clk_simple_probe(pdev);
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};
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static const struct of_device_id of_match_clk_mt7988_xfipll[] = {
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{ .compatible = "mediatek,mt7988-xfi-pll", .data = &xfipll_desc },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_xfipll);
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static struct platform_driver clk_mt7988_xfipll_drv = {
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.driver = {
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.name = "clk-mt7988-xfipll",
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.of_match_table = of_match_clk_mt7988_xfipll,
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},
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.probe = clk_mt7988_xfipll_probe,
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.remove = mtk_clk_simple_remove,
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};
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module_platform_driver(clk_mt7988_xfipll_drv);
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MODULE_DESCRIPTION("MediaTek MT7988 XFI PLL clock driver");
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MODULE_LICENSE("GPL");
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