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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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44a4ef59d5
While the GCC and Clang compilers already define __ASSEMBLER__ automatically when compiling assembly code, __ASSEMBLY__ is a macro that only gets defined by the Makefiles in the kernel. This can be very confusing when switching between userspace and kernelspace coding, or when dealing with uapi headers that rather should use __ASSEMBLER__ instead. So let's standardize on the __ASSEMBLER__ macro that is provided by the compilers now. This is a completely mechanical patch (done with a simple "sed -i" statement). Cc: Chris Zankel <chris@zankel.net> Cc: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20250314071013.1575167-40-thuth@redhat.com> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
156 lines
4.6 KiB
C
156 lines
4.6 KiB
C
/*
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* include/asm-xtensa/coprocessor.h
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2003 - 2007 Tensilica Inc.
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*/
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#ifndef _XTENSA_COPROCESSOR_H
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#define _XTENSA_COPROCESSOR_H
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#include <variant/tie.h>
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#include <asm/core.h>
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#include <asm/types.h>
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#ifdef __ASSEMBLER__
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# include <variant/tie-asm.h>
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.macro xchal_sa_start a b
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.set .Lxchal_pofs_, 0
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.set .Lxchal_ofs_, 0
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.endm
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.macro xchal_sa_align ptr minofs maxofs ofsalign totalign
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.set .Lxchal_ofs_, .Lxchal_ofs_ + .Lxchal_pofs_ + \totalign - 1
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.set .Lxchal_ofs_, (.Lxchal_ofs_ & -\totalign) - .Lxchal_pofs_
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.endm
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#define _SELECT ( XTHAL_SAS_TIE | XTHAL_SAS_OPT \
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| XTHAL_SAS_CC \
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| XTHAL_SAS_CALR | XTHAL_SAS_CALE )
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.macro save_xtregs_opt ptr clb at1 at2 at3 at4 offset
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.if XTREGS_OPT_SIZE > 0
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addi \clb, \ptr, \offset
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xchal_ncp_store \clb \at1 \at2 \at3 \at4 select=_SELECT
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.endif
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.endm
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.macro load_xtregs_opt ptr clb at1 at2 at3 at4 offset
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.if XTREGS_OPT_SIZE > 0
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addi \clb, \ptr, \offset
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xchal_ncp_load \clb \at1 \at2 \at3 \at4 select=_SELECT
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.endif
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.endm
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#undef _SELECT
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#define _SELECT ( XTHAL_SAS_TIE | XTHAL_SAS_OPT \
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| XTHAL_SAS_NOCC \
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| XTHAL_SAS_CALR | XTHAL_SAS_CALE | XTHAL_SAS_GLOB )
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.macro save_xtregs_user ptr clb at1 at2 at3 at4 offset
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.if XTREGS_USER_SIZE > 0
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addi \clb, \ptr, \offset
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xchal_ncp_store \clb \at1 \at2 \at3 \at4 select=_SELECT
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.endif
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.endm
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.macro load_xtregs_user ptr clb at1 at2 at3 at4 offset
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.if XTREGS_USER_SIZE > 0
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addi \clb, \ptr, \offset
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xchal_ncp_load \clb \at1 \at2 \at3 \at4 select=_SELECT
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.endif
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.endm
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#undef _SELECT
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#endif /* __ASSEMBLER__ */
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/*
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* XTENSA_HAVE_COPROCESSOR(x) returns 1 if coprocessor x is configured.
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*
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* XTENSA_HAVE_IO_PORT(x) returns 1 if io-port x is configured.
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*
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*/
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#define XTENSA_HAVE_COPROCESSOR(x) \
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((XCHAL_CP_MASK ^ XCHAL_CP_PORT_MASK) & (1 << (x)))
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#define XTENSA_HAVE_COPROCESSORS \
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(XCHAL_CP_MASK ^ XCHAL_CP_PORT_MASK)
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#define XTENSA_HAVE_IO_PORT(x) \
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(XCHAL_CP_PORT_MASK & (1 << (x)))
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#define XTENSA_HAVE_IO_PORTS \
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XCHAL_CP_PORT_MASK
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#ifndef __ASSEMBLER__
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/*
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* Additional registers.
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* We define three types of additional registers:
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* ext: extra registers that are used by the compiler
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* cpn: optional registers that can be used by a user application
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* cpX: coprocessor registers that can only be used if the corresponding
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* CPENABLE bit is set.
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*/
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#define XCHAL_SA_REG(list,cc,abi,type,y,name,z,align,size,...) \
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__REG ## list (cc, abi, type, name, size, align)
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#define __REG0(cc,abi,t,name,s,a) __REG0_ ## cc (abi,name)
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#define __REG1(cc,abi,t,name,s,a) __REG1_ ## cc (name)
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#define __REG2(cc,abi,type,...) __REG2_ ## type (__VA_ARGS__)
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#define __REG0_0(abi,name)
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#define __REG0_1(abi,name) __REG0_1 ## abi (name)
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#define __REG0_10(name) __u32 name;
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#define __REG0_11(name) __u32 name;
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#define __REG0_12(name)
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#define __REG1_0(name) __u32 name;
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#define __REG1_1(name)
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#define __REG2_0(n,s,a) __u32 name;
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#define __REG2_1(n,s,a) unsigned char n[s] __attribute__ ((aligned(a)));
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#define __REG2_2(n,s,a) unsigned char n[s] __attribute__ ((aligned(a)));
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typedef struct { XCHAL_NCP_SA_LIST(0) } xtregs_opt_t
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__attribute__ ((aligned (XCHAL_NCP_SA_ALIGN)));
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typedef struct { XCHAL_NCP_SA_LIST(1) } xtregs_user_t
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__attribute__ ((aligned (XCHAL_NCP_SA_ALIGN)));
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#if XTENSA_HAVE_COPROCESSORS
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typedef struct { XCHAL_CP0_SA_LIST(2) } xtregs_cp0_t
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__attribute__ ((aligned (XCHAL_CP0_SA_ALIGN)));
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typedef struct { XCHAL_CP1_SA_LIST(2) } xtregs_cp1_t
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__attribute__ ((aligned (XCHAL_CP1_SA_ALIGN)));
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typedef struct { XCHAL_CP2_SA_LIST(2) } xtregs_cp2_t
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__attribute__ ((aligned (XCHAL_CP2_SA_ALIGN)));
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typedef struct { XCHAL_CP3_SA_LIST(2) } xtregs_cp3_t
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__attribute__ ((aligned (XCHAL_CP3_SA_ALIGN)));
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typedef struct { XCHAL_CP4_SA_LIST(2) } xtregs_cp4_t
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__attribute__ ((aligned (XCHAL_CP4_SA_ALIGN)));
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typedef struct { XCHAL_CP5_SA_LIST(2) } xtregs_cp5_t
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__attribute__ ((aligned (XCHAL_CP5_SA_ALIGN)));
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typedef struct { XCHAL_CP6_SA_LIST(2) } xtregs_cp6_t
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__attribute__ ((aligned (XCHAL_CP6_SA_ALIGN)));
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typedef struct { XCHAL_CP7_SA_LIST(2) } xtregs_cp7_t
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__attribute__ ((aligned (XCHAL_CP7_SA_ALIGN)));
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struct thread_info;
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void coprocessor_flush(struct thread_info *ti, int cp_index);
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void coprocessor_release_all(struct thread_info *ti);
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void coprocessor_flush_all(struct thread_info *ti);
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void coprocessor_flush_release_all(struct thread_info *ti);
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void local_coprocessors_flush_release_all(void);
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#endif /* XTENSA_HAVE_COPROCESSORS */
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#endif /* !__ASSEMBLER__ */
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#endif /* _XTENSA_COPROCESSOR_H */
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