mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-03 01:28:04 +00:00
b7cf2a1d98
xtensa's flush_dcache_page() can be a no-op sometimes. There is a
generic implementation for this case in include/asm-generic/
cacheflush.h.
#ifndef ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE
static inline void flush_dcache_page(struct page *page)
{
}
#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
#endif
So remove the superfluous flush_dcache_page() definition, which also
helps silence potential build warnings complaining the page variable
passed to flush_dcache_page() is not used.
In file included from crypto/scompress.c:12:
include/crypto/scatterwalk.h: In function 'scatterwalk_pagedone':
include/crypto/scatterwalk.h:76:30: warning: variable 'page' set but not used [-Wunused-but-set-variable]
76 | struct page *page;
| ^~~~
crypto/scompress.c: In function 'scomp_acomp_comp_decomp':
>> crypto/scompress.c:174:38: warning: unused variable 'dst_page' [-Wunused-variable]
174 | struct page *dst_page = sg_page(req->dst);
|
The issue was originally reported on LoongArch by kernel test
robot (Huacai fixed it on LoongArch), then reported by Guenter
and me on xtensa.
This patch also removes lots of redundant macros which have
been defined by asm-generic/cacheflush.h.
Cc: Huacai Chen <chenhuacai@loongson.cn>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202403091614.NeUw5zcv-lkp@intel.com/
Reported-by: Barry Song <v-songbaohua@oppo.com>
Closes: https://lore.kernel.org/all/CAGsJ_4yDk1+axbte7FKQEwD7X2oxUCFrEc9M5YOS1BobfDFXPA@mail.gmail.com/
Reported-by: Guenter Roeck <linux@roeck-us.net>
Closes: https://lore.kernel.org/all/aaa8b7d7-5abe-47bf-93f6-407942436472@roeck-us.net/
Fixes: 77292bb8ca ("crypto: scomp - remove memcpy if sg_nents is 1 and pages are lowmem")
Signed-off-by: Barry Song <v-songbaohua@oppo.com>
Message-Id: <20240319010920.125192-1-21cnbao@gmail.com>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
182 lines
5.6 KiB
C
182 lines
5.6 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* (C) 2001 - 2013 Tensilica Inc.
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*/
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#ifndef _XTENSA_CACHEFLUSH_H
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#define _XTENSA_CACHEFLUSH_H
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#include <linux/mm.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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/*
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* Lo-level routines for cache flushing.
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*
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* invalidate data or instruction cache:
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*
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* __invalidate_icache_all()
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* __invalidate_icache_page(adr)
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* __invalidate_dcache_page(adr)
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* __invalidate_icache_range(from,size)
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* __invalidate_dcache_range(from,size)
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*
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* flush data cache:
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*
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* __flush_dcache_page(adr)
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*
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* flush and invalidate data cache:
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*
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* __flush_invalidate_dcache_all()
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* __flush_invalidate_dcache_page(adr)
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* __flush_invalidate_dcache_range(from,size)
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*
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* specials for cache aliasing:
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*
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* __flush_invalidate_dcache_page_alias(vaddr,paddr)
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* __invalidate_dcache_page_alias(vaddr,paddr)
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* __invalidate_icache_page_alias(vaddr,paddr)
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*/
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extern void __invalidate_dcache_all(void);
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extern void __invalidate_icache_all(void);
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extern void __invalidate_dcache_page(unsigned long);
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extern void __invalidate_icache_page(unsigned long);
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extern void __invalidate_icache_range(unsigned long, unsigned long);
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extern void __invalidate_dcache_range(unsigned long, unsigned long);
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#if XCHAL_DCACHE_IS_WRITEBACK
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extern void __flush_invalidate_dcache_all(void);
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extern void __flush_dcache_page(unsigned long);
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extern void __flush_dcache_range(unsigned long, unsigned long);
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extern void __flush_invalidate_dcache_page(unsigned long);
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extern void __flush_invalidate_dcache_range(unsigned long, unsigned long);
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#else
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static inline void __flush_dcache_page(unsigned long va)
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{
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}
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static inline void __flush_dcache_range(unsigned long va, unsigned long sz)
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{
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}
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# define __flush_invalidate_dcache_all() __invalidate_dcache_all()
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# define __flush_invalidate_dcache_page(p) __invalidate_dcache_page(p)
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# define __flush_invalidate_dcache_range(p,s) __invalidate_dcache_range(p,s)
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#endif
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#if defined(CONFIG_MMU) && (DCACHE_WAY_SIZE > PAGE_SIZE)
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extern void __flush_invalidate_dcache_page_alias(unsigned long, unsigned long);
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extern void __invalidate_dcache_page_alias(unsigned long, unsigned long);
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#else
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static inline void __flush_invalidate_dcache_page_alias(unsigned long virt,
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unsigned long phys) { }
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static inline void __invalidate_dcache_page_alias(unsigned long virt,
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unsigned long phys) { }
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#endif
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#if defined(CONFIG_MMU) && (ICACHE_WAY_SIZE > PAGE_SIZE)
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extern void __invalidate_icache_page_alias(unsigned long, unsigned long);
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#else
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static inline void __invalidate_icache_page_alias(unsigned long virt,
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unsigned long phys) { }
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#endif
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/*
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* We have physically tagged caches - nothing to do here -
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* unless we have cache aliasing.
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*
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* Pages can get remapped. Because this might change the 'color' of that page,
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* we have to flush the cache before the PTE is changed.
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* (see also Documentation/core-api/cachetlb.rst)
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*/
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#if defined(CONFIG_MMU) && \
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((DCACHE_WAY_SIZE > PAGE_SIZE) || defined(CONFIG_SMP))
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#ifdef CONFIG_SMP
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void flush_cache_all(void);
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void flush_cache_range(struct vm_area_struct*, ulong, ulong);
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void flush_icache_range(unsigned long start, unsigned long end);
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void flush_cache_page(struct vm_area_struct*,
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unsigned long, unsigned long);
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#define flush_cache_all flush_cache_all
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#define flush_cache_range flush_cache_range
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#define flush_icache_range flush_icache_range
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#define flush_cache_page flush_cache_page
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#else
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#define flush_cache_all local_flush_cache_all
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#define flush_cache_range local_flush_cache_range
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#define flush_icache_range local_flush_icache_range
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#define flush_cache_page local_flush_cache_page
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#endif
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#define local_flush_cache_all() \
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do { \
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__flush_invalidate_dcache_all(); \
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__invalidate_icache_all(); \
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} while (0)
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#define flush_cache_mm(mm) flush_cache_all()
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#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
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#define flush_cache_vmap(start,end) flush_cache_all()
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#define flush_cache_vmap_early(start,end) do { } while (0)
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#define flush_cache_vunmap(start,end) flush_cache_all()
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void flush_dcache_folio(struct folio *folio);
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#define flush_dcache_folio flush_dcache_folio
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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static inline void flush_dcache_page(struct page *page)
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{
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flush_dcache_folio(page_folio(page));
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}
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void local_flush_cache_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end);
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void local_flush_cache_page(struct vm_area_struct *vma,
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unsigned long address, unsigned long pfn);
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#else
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#define flush_icache_range local_flush_icache_range
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#endif
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#define flush_icache_user_range flush_icache_range
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/* Ensure consistency between data and instruction cache. */
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#define local_flush_icache_range(start, end) \
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do { \
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__flush_dcache_range(start, (end) - (start)); \
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__invalidate_icache_range(start,(end) - (start)); \
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} while (0)
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#if defined(CONFIG_MMU) && (DCACHE_WAY_SIZE > PAGE_SIZE)
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extern void copy_to_user_page(struct vm_area_struct*, struct page*,
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unsigned long, void*, const void*, unsigned long);
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extern void copy_from_user_page(struct vm_area_struct*, struct page*,
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unsigned long, void*, const void*, unsigned long);
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#define copy_to_user_page copy_to_user_page
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#define copy_from_user_page copy_from_user_page
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#else
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#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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memcpy(dst, src, len); \
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__flush_dcache_range((unsigned long) dst, len); \
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__invalidate_icache_range((unsigned long) dst, len); \
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} while (0)
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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memcpy(dst, src, len)
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#endif
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#include <asm-generic/cacheflush.h>
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#endif /* _XTENSA_CACHEFLUSH_H */
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