mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-01 15:14:52 +00:00
2f24482304
There is new support for additional on-chip devices on Apple, Mediatek,
Renesas, Rockchip, Samsung, Google, TI, ST, Nvidia and Amlogic devices.
The Arm Morello reference platform gets a devicetree for booting in
normal aarch64 mode. The hardware supports experimental CHERI support,
which requires a modified kernel.
The AMD (formerly Xilinx) Versal NET SoC gets added, this is a combined
FPGA with Cortex-A78 CPUs in a SoC.
Six new ST STM32MP2 SoC variants are added. Like the earlier STM32MP25,
the MP211, MP213, MP215, MP231, MP233 and MP235 models are based on one
or two Cortex-A35 cores but each feature a different set of I/O devices.
Mediatek MT8370 is a minor variation of MT8390 with fewer CPU and
GPU cores
Apple T2 is the baseboard management controller on earlier Intel CPU
based Macs, with 16 models now gaining initial support.
All the above come with dts files for the reference boards. In
addition, these boards are added for the SoCs that are already supported.
- The Milk-V Jupiter board based on SpacemiT K1/M1
- NetCube Systems Kumquat board based on the 32-bit Allwinner V3s SoC
- Three boards based on 32-bit stm32mp1
- 11 distinct board variants from Toradex and one from Variscite,
all based on i.MX6
- Google Pixel Pro 6 phone based on gs101 (Tensor)
- Three additional variants of the i.MX8MP based "Skov" board
- A second variant of the i.MX95 EVK board
- Two boards based on Renesas SoCs
- Four boards based the Rockchip RK35xx series, plus the RK3588
"MNT Reform 2" laptop
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Merge tag 'soc-dt-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC devicetree updates from Arnd Bergmann:
"There is new support for additional on-chip devices on Apple,
Mediatek, Renesas, Rockchip, Samsung, Google, TI, ST, Nvidia and
Amlogic devices.
The Arm Morello reference platform gets a devicetree for booting in
normal aarch64 mode. The hardware supports experimental CHERI support,
which requires a modified kernel.
The AMD (formerly Xilinx) Versal NET SoC gets added, this is a
combined FPGA with Cortex-A78 CPUs in a SoC.
Six new ST STM32MP2 SoC variants are added. Like the earlier
STM32MP25, the MP211, MP213, MP215, MP231, MP233 and MP235 models are
based on one or two Cortex-A35 cores but each feature a different set
of I/O devices.
Mediatek MT8370 is a minor variation of MT8390 with fewer CPU and GPU
cores
Apple T2 is the baseboard management controller on earlier Intel CPU
based Macs, with 16 models now gaining initial support.
All the above come with dts files for the reference boards. In
addition, these boards are added for the SoCs that are already
supported:
- The Milk-V Jupiter board based on SpacemiT K1/M1
- NetCube Systems Kumquat board based on the 32-bit Allwinner V3s SoC
- Three boards based on 32-bit stm32mp1
- 11 distinct board variants from Toradex and one from Variscite, all
based on i.MX6
- Google Pixel Pro 6 phone based on gs101 (Tensor)
- Three additional variants of the i.MX8MP based "Skov" board
- A second variant of the i.MX95 EVK board
- Two boards based on Renesas SoCs
- Four boards based the Rockchip RK35xx series, plus the RK3588 'MNT
Reform 2' laptop"
* tag 'soc-dt-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (538 commits)
arm64: dts: Add gpio_intc node for Amlogic A5 SoCs
arm64: dts: Add gpio_intc node for Amlogic A4 SoCs
arm64: dts: hi3660: Add property for fixing CPUIdle
arm64: dts: rockchip: remove ethm0_clk0_25m_out from Sige5 gmac0
arm64: dts: marvell: Use preferred node names for "simple-bus"
arm64: dts: marvell: Drop unused CP11X_TYPE define
arm64: dts: marvell: Move arch timer and pmu nodes to top-level
arm64: dts: rockchip: Fix PWM pinctrl names
arm64: dts: rockchip: fix RK3576 SCMI clock IDs
dt-bindings: clock: rk3576: add SCMI clocks
arm64: dts: rockchip: Fix pcie reset gpio on Orange Pi 5 Max
arm64: dts: amd/seattle: Drop undocumented "spi-controller" properties
arm64: dts: amd/seattle: Fix bus, mmc, and ethernet node names
arm64: dts: amd/seattle: Move and simplify fixed clocks
arm64: dts: amd/seattle: Base Overdrive B1 on top of B0 version
arm64: dts: rockchip: Enable HDMI audio output for ArmSoM Sige7
arm64: dts: rockchip: Enable onboard eMMC on Radxa E20C
arm64: dts: rockchip: Add SDHCI controller for RK3528
arm64: dts: rockchip: Remove bluetooth node from rock-3a
arm64: dts: rockchip: Move rk356x scmi SHMEM to reserved memory
...
1311 lines
37 KiB
Plaintext
1311 lines
37 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0 OR MIT
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/*
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* Copyright (C) 2022 StarFive Technology Co., Ltd.
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* Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
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*/
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/dts-v1/;
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#include <dt-bindings/clock/starfive,jh7110-crg.h>
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#include <dt-bindings/power/starfive,jh7110-pmu.h>
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#include <dt-bindings/reset/starfive,jh7110-crg.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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compatible = "starfive,jh7110";
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#address-cells = <2>;
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#size-cells = <2>;
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cpus: cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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S7_0: cpu@0 {
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compatible = "sifive,s7", "riscv";
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reg = <0>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <16384>;
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next-level-cache = <&ccache>;
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riscv,isa = "rv64imac_zba_zbb";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "c", "zba", "zbb", "zicntr", "zicsr",
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"zifencei", "zihpm";
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status = "disabled";
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cpu0_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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U74_1: cpu@1 {
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compatible = "sifive,u74-mc", "riscv";
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reg = <1>;
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <40>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <40>;
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mmu-type = "riscv,sv39";
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next-level-cache = <&ccache>;
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riscv,isa = "rv64imafdc_zba_zbb";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
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"zicsr", "zifencei", "zihpm";
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tlb-split;
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operating-points-v2 = <&cpu_opp>;
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clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
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clock-names = "cpu";
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#cooling-cells = <2>;
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cpu1_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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U74_2: cpu@2 {
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compatible = "sifive,u74-mc", "riscv";
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reg = <2>;
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <40>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <40>;
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mmu-type = "riscv,sv39";
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next-level-cache = <&ccache>;
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riscv,isa = "rv64imafdc_zba_zbb";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
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"zicsr", "zifencei", "zihpm";
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tlb-split;
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operating-points-v2 = <&cpu_opp>;
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clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
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clock-names = "cpu";
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#cooling-cells = <2>;
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cpu2_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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U74_3: cpu@3 {
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compatible = "sifive,u74-mc", "riscv";
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reg = <3>;
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <40>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <40>;
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mmu-type = "riscv,sv39";
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next-level-cache = <&ccache>;
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riscv,isa = "rv64imafdc_zba_zbb";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
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"zicsr", "zifencei", "zihpm";
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tlb-split;
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operating-points-v2 = <&cpu_opp>;
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clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
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clock-names = "cpu";
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#cooling-cells = <2>;
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cpu3_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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U74_4: cpu@4 {
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compatible = "sifive,u74-mc", "riscv";
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reg = <4>;
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <40>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <40>;
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mmu-type = "riscv,sv39";
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next-level-cache = <&ccache>;
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riscv,isa = "rv64imafdc_zba_zbb";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
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"zicsr", "zifencei", "zihpm";
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tlb-split;
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operating-points-v2 = <&cpu_opp>;
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clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
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clock-names = "cpu";
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#cooling-cells = <2>;
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cpu4_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&S7_0>;
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};
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core1 {
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cpu = <&U74_1>;
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};
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core2 {
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cpu = <&U74_2>;
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};
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core3 {
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cpu = <&U74_3>;
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};
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core4 {
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cpu = <&U74_4>;
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};
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};
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};
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};
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cpu_opp: opp-table-0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-375000000 {
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opp-hz = /bits/ 64 <375000000>;
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opp-microvolt = <800000>;
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};
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opp-500000000 {
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opp-hz = /bits/ 64 <500000000>;
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opp-microvolt = <800000>;
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};
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opp-750000000 {
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opp-hz = /bits/ 64 <750000000>;
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opp-microvolt = <800000>;
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};
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opp-1500000000 {
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opp-hz = /bits/ 64 <1500000000>;
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opp-microvolt = <1040000>;
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};
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};
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thermal-zones {
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cpu-thermal {
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polling-delay-passive = <250>;
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polling-delay = <15000>;
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thermal-sensors = <&sfctemp>;
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cooling-maps {
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map0 {
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trip = <&cpu_alert0>;
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cooling-device =
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<&U74_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&U74_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&U74_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&U74_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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trips {
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cpu_alert0: cpu-alert0 {
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/* milliCelsius */
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu-crit {
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/* milliCelsius */
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temperature = <100000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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};
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dvp_clk: dvp-clock {
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compatible = "fixed-clock";
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clock-output-names = "dvp_clk";
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#clock-cells = <0>;
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};
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gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
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compatible = "fixed-clock";
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clock-output-names = "gmac0_rgmii_rxin";
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#clock-cells = <0>;
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};
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gmac0_rmii_refin: gmac0-rmii-refin-clock {
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compatible = "fixed-clock";
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clock-output-names = "gmac0_rmii_refin";
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#clock-cells = <0>;
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};
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gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock {
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compatible = "fixed-clock";
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clock-output-names = "gmac1_rgmii_rxin";
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#clock-cells = <0>;
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};
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gmac1_rmii_refin: gmac1-rmii-refin-clock {
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compatible = "fixed-clock";
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clock-output-names = "gmac1_rmii_refin";
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#clock-cells = <0>;
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};
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hdmitx0_pixelclk: hdmitx0-pixel-clock {
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compatible = "fixed-clock";
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clock-output-names = "hdmitx0_pixelclk";
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#clock-cells = <0>;
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};
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i2srx_bclk_ext: i2srx-bclk-ext-clock {
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compatible = "fixed-clock";
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clock-output-names = "i2srx_bclk_ext";
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#clock-cells = <0>;
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};
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i2srx_lrck_ext: i2srx-lrck-ext-clock {
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compatible = "fixed-clock";
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clock-output-names = "i2srx_lrck_ext";
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#clock-cells = <0>;
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};
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i2stx_bclk_ext: i2stx-bclk-ext-clock {
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compatible = "fixed-clock";
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clock-output-names = "i2stx_bclk_ext";
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#clock-cells = <0>;
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};
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i2stx_lrck_ext: i2stx-lrck-ext-clock {
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compatible = "fixed-clock";
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clock-output-names = "i2stx_lrck_ext";
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#clock-cells = <0>;
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};
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mclk_ext: mclk-ext-clock {
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compatible = "fixed-clock";
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clock-output-names = "mclk_ext";
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#clock-cells = <0>;
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};
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osc: oscillator {
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compatible = "fixed-clock";
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clock-output-names = "osc";
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#clock-cells = <0>;
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};
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rtc_osc: rtc-oscillator {
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compatible = "fixed-clock";
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clock-output-names = "rtc_osc";
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#clock-cells = <0>;
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};
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stmmac_axi_setup: stmmac-axi-config {
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snps,lpi_en;
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snps,wr_osr_lmt = <15>;
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snps,rd_osr_lmt = <15>;
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snps,blen = <256 128 64 32 0 0 0>;
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};
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tdm_ext: tdm-ext-clock {
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compatible = "fixed-clock";
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clock-output-names = "tdm_ext";
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#clock-cells = <0>;
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&plic>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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clint: timer@2000000 {
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compatible = "starfive,jh7110-clint", "sifive,clint0";
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reg = <0x0 0x2000000 0x0 0x10000>;
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interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
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<&cpu1_intc 3>, <&cpu1_intc 7>,
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<&cpu2_intc 3>, <&cpu2_intc 7>,
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<&cpu3_intc 3>, <&cpu3_intc 7>,
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<&cpu4_intc 3>, <&cpu4_intc 7>;
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};
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ccache: cache-controller@2010000 {
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compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache";
|
|
reg = <0x0 0x2010000 0x0 0x4000>;
|
|
interrupts = <1>, <3>, <4>, <2>;
|
|
cache-block-size = <64>;
|
|
cache-level = <2>;
|
|
cache-sets = <2048>;
|
|
cache-size = <2097152>;
|
|
cache-unified;
|
|
};
|
|
|
|
plic: interrupt-controller@c000000 {
|
|
compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
|
|
reg = <0x0 0xc000000 0x0 0x4000000>;
|
|
interrupts-extended = <&cpu0_intc 11>,
|
|
<&cpu1_intc 11>, <&cpu1_intc 9>,
|
|
<&cpu2_intc 11>, <&cpu2_intc 9>,
|
|
<&cpu3_intc 11>, <&cpu3_intc 9>,
|
|
<&cpu4_intc 11>, <&cpu4_intc 9>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
#address-cells = <0>;
|
|
riscv,ndev = <136>;
|
|
};
|
|
|
|
uart0: serial@10000000 {
|
|
compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
|
|
reg = <0x0 0x10000000 0x0 0x10000>;
|
|
clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>,
|
|
<&syscrg JH7110_SYSCLK_UART0_APB>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
resets = <&syscrg JH7110_SYSRST_UART0_APB>,
|
|
<&syscrg JH7110_SYSRST_UART0_CORE>;
|
|
interrupts = <32>;
|
|
reg-io-width = <4>;
|
|
reg-shift = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@10010000 {
|
|
compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
|
|
reg = <0x0 0x10010000 0x0 0x10000>;
|
|
clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>,
|
|
<&syscrg JH7110_SYSCLK_UART1_APB>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
resets = <&syscrg JH7110_SYSRST_UART1_APB>,
|
|
<&syscrg JH7110_SYSRST_UART1_CORE>;
|
|
interrupts = <33>;
|
|
reg-io-width = <4>;
|
|
reg-shift = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@10020000 {
|
|
compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
|
|
reg = <0x0 0x10020000 0x0 0x10000>;
|
|
clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>,
|
|
<&syscrg JH7110_SYSCLK_UART2_APB>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
resets = <&syscrg JH7110_SYSRST_UART2_APB>,
|
|
<&syscrg JH7110_SYSRST_UART2_CORE>;
|
|
interrupts = <34>;
|
|
reg-io-width = <4>;
|
|
reg-shift = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@10030000 {
|
|
compatible = "snps,designware-i2c";
|
|
reg = <0x0 0x10030000 0x0 0x10000>;
|
|
clocks = <&syscrg JH7110_SYSCLK_I2C0_APB>;
|
|
clock-names = "ref";
|
|
resets = <&syscrg JH7110_SYSRST_I2C0_APB>;
|
|
interrupts = <35>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@10040000 {
|
|
compatible = "snps,designware-i2c";
|
|
reg = <0x0 0x10040000 0x0 0x10000>;
|
|
clocks = <&syscrg JH7110_SYSCLK_I2C1_APB>;
|
|
clock-names = "ref";
|
|
resets = <&syscrg JH7110_SYSRST_I2C1_APB>;
|
|
interrupts = <36>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@10050000 {
|
|
compatible = "snps,designware-i2c";
|
|
reg = <0x0 0x10050000 0x0 0x10000>;
|
|
clocks = <&syscrg JH7110_SYSCLK_I2C2_APB>;
|
|
clock-names = "ref";
|
|
resets = <&syscrg JH7110_SYSRST_I2C2_APB>;
|
|
interrupts = <37>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi0: spi@10060000 {
|
|
compatible = "arm,pl022", "arm,primecell";
|
|
reg = <0x0 0x10060000 0x0 0x10000>;
|
|
clocks = <&syscrg JH7110_SYSCLK_SPI0_APB>,
|
|
<&syscrg JH7110_SYSCLK_SPI0_APB>;
|
|
clock-names = "sspclk", "apb_pclk";
|
|
resets = <&syscrg JH7110_SYSRST_SPI0_APB>;
|
|
interrupts = <38>;
|
|
arm,primecell-periphid = <0x00041022>;
|
|
num-cs = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi1: spi@10070000 {
|
|
compatible = "arm,pl022", "arm,primecell";
|
|
reg = <0x0 0x10070000 0x0 0x10000>;
|
|
clocks = <&syscrg JH7110_SYSCLK_SPI1_APB>,
|
|
<&syscrg JH7110_SYSCLK_SPI1_APB>;
|
|
clock-names = "sspclk", "apb_pclk";
|
|
resets = <&syscrg JH7110_SYSRST_SPI1_APB>;
|
|
interrupts = <39>;
|
|
arm,primecell-periphid = <0x00041022>;
|
|
num-cs = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi2: spi@10080000 {
|
|
compatible = "arm,pl022", "arm,primecell";
|
|
reg = <0x0 0x10080000 0x0 0x10000>;
|
|
clocks = <&syscrg JH7110_SYSCLK_SPI2_APB>,
|
|
<&syscrg JH7110_SYSCLK_SPI2_APB>;
|
|
clock-names = "sspclk", "apb_pclk";
|
|
resets = <&syscrg JH7110_SYSRST_SPI2_APB>;
|
|
interrupts = <40>;
|
|
arm,primecell-periphid = <0x00041022>;
|
|
num-cs = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tdm: tdm@10090000 {
|
|
compatible = "starfive,jh7110-tdm";
|
|
reg = <0x0 0x10090000 0x0 0x1000>;
|
|
clocks = <&syscrg JH7110_SYSCLK_TDM_AHB>,
|
|
<&syscrg JH7110_SYSCLK_TDM_APB>,
|
|
<&syscrg JH7110_SYSCLK_TDM_INTERNAL>,
|
|
<&syscrg JH7110_SYSCLK_TDM_TDM>,
|
|
<&syscrg JH7110_SYSCLK_MCLK_INNER>,
|
|
<&tdm_ext>;
|
|
clock-names = "tdm_ahb", "tdm_apb",
|
|
"tdm_internal", "tdm",
|
|
"mclk_inner", "tdm_ext";
|
|
resets = <&syscrg JH7110_SYSRST_TDM_AHB>,
|
|
<&syscrg JH7110_SYSRST_TDM_APB>,
|
|
<&syscrg JH7110_SYSRST_TDM_CORE>;
|
|
dmas = <&dma 20>, <&dma 21>;
|
|
dma-names = "rx","tx";
|
|
#sound-dai-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2srx: i2s@100e0000 {
|
|
compatible = "starfive,jh7110-i2srx";
|
|
reg = <0x0 0x100e0000 0x0 0x1000>;
|
|
clocks = <&syscrg JH7110_SYSCLK_I2SRX_BCLK_MST>,
|
|
<&syscrg JH7110_SYSCLK_I2SRX_APB>,
|
|
<&syscrg JH7110_SYSCLK_MCLK>,
|
|
<&syscrg JH7110_SYSCLK_MCLK_INNER>,
|
|
<&mclk_ext>,
|
|
<&syscrg JH7110_SYSCLK_I2SRX_BCLK>,
|
|
<&syscrg JH7110_SYSCLK_I2SRX_LRCK>,
|
|
<&i2srx_bclk_ext>,
|
|
<&i2srx_lrck_ext>;
|
|
clock-names = "i2sclk", "apb", "mclk",
|
|
"mclk_inner", "mclk_ext", "bclk",
|
|
"lrck", "bclk_ext", "lrck_ext";
|
|
resets = <&syscrg JH7110_SYSRST_I2SRX_APB>,
|
|
<&syscrg JH7110_SYSRST_I2SRX_BCLK>;
|
|
dmas = <0>, <&dma 24>;
|
|
dma-names = "tx", "rx";
|
|
starfive,syscon = <&sys_syscon 0x18 0x2>;
|
|
#sound-dai-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwmdac: pwmdac@100b0000 {
|
|
compatible = "starfive,jh7110-pwmdac";
|
|
reg = <0x0 0x100b0000 0x0 0x1000>;
|
|
clocks = <&syscrg JH7110_SYSCLK_PWMDAC_APB>,
|
|
<&syscrg JH7110_SYSCLK_PWMDAC_CORE>;
|
|
clock-names = "apb", "core";
|
|
resets = <&syscrg JH7110_SYSRST_PWMDAC_APB>;
|
|
dmas = <&dma 22>;
|
|
dma-names = "tx";
|
|
#sound-dai-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb0: usb@10100000 {
|
|
compatible = "starfive,jh7110-usb";
|
|
ranges = <0x0 0x0 0x10100000 0x100000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
starfive,stg-syscon = <&stg_syscon 0x4>;
|
|
clocks = <&stgcrg JH7110_STGCLK_USB0_LPM>,
|
|
<&stgcrg JH7110_STGCLK_USB0_STB>,
|
|
<&stgcrg JH7110_STGCLK_USB0_APB>,
|
|
<&stgcrg JH7110_STGCLK_USB0_AXI>,
|
|
<&stgcrg JH7110_STGCLK_USB0_UTMI_APB>;
|
|
clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
|
|
resets = <&stgcrg JH7110_STGRST_USB0_PWRUP>,
|
|
<&stgcrg JH7110_STGRST_USB0_APB>,
|
|
<&stgcrg JH7110_STGRST_USB0_AXI>,
|
|
<&stgcrg JH7110_STGRST_USB0_UTMI_APB>;
|
|
reset-names = "pwrup", "apb", "axi", "utmi_apb";
|
|
status = "disabled";
|
|
|
|
usb_cdns3: usb@0 {
|
|
compatible = "cdns,usb3";
|
|
reg = <0x0 0x10000>,
|
|
<0x10000 0x10000>,
|
|
<0x20000 0x10000>;
|
|
reg-names = "otg", "xhci", "dev";
|
|
interrupts = <100>, <108>, <110>;
|
|
interrupt-names = "host", "peripheral", "otg";
|
|
phys = <&usbphy0>;
|
|
phy-names = "cdns3,usb2-phy";
|
|
};
|
|
};
|
|
|
|
usbphy0: phy@10200000 {
|
|
compatible = "starfive,jh7110-usb-phy";
|
|
reg = <0x0 0x10200000 0x0 0x10000>;
|
|
clocks = <&syscrg JH7110_SYSCLK_USB_125M>,
|
|
<&stgcrg JH7110_STGCLK_USB0_APP_125>;
|
|
clock-names = "125m", "app_125m";
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
pciephy0: phy@10210000 {
|
|
compatible = "starfive,jh7110-pcie-phy";
|
|
reg = <0x0 0x10210000 0x0 0x10000>;
|
|
starfive,sys-syscon = <&sys_syscon 0x18>;
|
|
starfive,stg-syscon = <&stg_syscon 0x148 0x1f4>;
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
pciephy1: phy@10220000 {
|
|
compatible = "starfive,jh7110-pcie-phy";
|
|
reg = <0x0 0x10220000 0x0 0x10000>;
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
stgcrg: clock-controller@10230000 {
|
|
compatible = "starfive,jh7110-stgcrg";
|
|
reg = <0x0 0x10230000 0x0 0x10000>;
|
|
clocks = <&osc>,
|
|
<&syscrg JH7110_SYSCLK_HIFI4_CORE>,
|
|
<&syscrg JH7110_SYSCLK_STG_AXIAHB>,
|
|
<&syscrg JH7110_SYSCLK_USB_125M>,
|
|
<&syscrg JH7110_SYSCLK_CPU_BUS>,
|
|
<&syscrg JH7110_SYSCLK_HIFI4_AXI>,
|
|
<&syscrg JH7110_SYSCLK_NOCSTG_BUS>,
|
|
<&syscrg JH7110_SYSCLK_APB_BUS>;
|
|
clock-names = "osc", "hifi4_core",
|
|
"stg_axiahb", "usb_125m",
|
|
"cpu_bus", "hifi4_axi",
|
|
"nocstg_bus", "apb_bus";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
stg_syscon: syscon@10240000 {
|
|
compatible = "starfive,jh7110-stg-syscon", "syscon";
|
|
reg = <0x0 0x10240000 0x0 0x1000>;
|
|
};
|
|
|
|
uart3: serial@12000000 {
|
|
compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
|
|
reg = <0x0 0x12000000 0x0 0x10000>;
|
|
clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>,
|
|
<&syscrg JH7110_SYSCLK_UART3_APB>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
resets = <&syscrg JH7110_SYSRST_UART3_APB>,
|
|
<&syscrg JH7110_SYSRST_UART3_CORE>;
|
|
interrupts = <45>;
|
|
reg-io-width = <4>;
|
|
reg-shift = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@12010000 {
|
|
compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
|
|
reg = <0x0 0x12010000 0x0 0x10000>;
|
|
clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>,
|
|
<&syscrg JH7110_SYSCLK_UART4_APB>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
resets = <&syscrg JH7110_SYSRST_UART4_APB>,
|
|
<&syscrg JH7110_SYSRST_UART4_CORE>;
|
|
interrupts = <46>;
|
|
reg-io-width = <4>;
|
|
reg-shift = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart5: serial@12020000 {
|
|
compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
|
|
reg = <0x0 0x12020000 0x0 0x10000>;
|
|
clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>,
|
|
<&syscrg JH7110_SYSCLK_UART5_APB>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
resets = <&syscrg JH7110_SYSRST_UART5_APB>,
|
|
<&syscrg JH7110_SYSRST_UART5_CORE>;
|
|
interrupts = <47>;
|
|
reg-io-width = <4>;
|
|
reg-shift = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@12030000 {
|
|
compatible = "snps,designware-i2c";
|
|
reg = <0x0 0x12030000 0x0 0x10000>;
|
|
clocks = <&syscrg JH7110_SYSCLK_I2C3_APB>;
|
|
clock-names = "ref";
|
|
resets = <&syscrg JH7110_SYSRST_I2C3_APB>;
|
|
interrupts = <48>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c4: i2c@12040000 {
|
|
compatible = "snps,designware-i2c";
|
|
reg = <0x0 0x12040000 0x0 0x10000>;
|
|
clocks = <&syscrg JH7110_SYSCLK_I2C4_APB>;
|
|
clock-names = "ref";
|
|
resets = <&syscrg JH7110_SYSRST_I2C4_APB>;
|
|
interrupts = <49>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c5: i2c@12050000 {
|
|
compatible = "snps,designware-i2c";
|
|
reg = <0x0 0x12050000 0x0 0x10000>;
|
|
clocks = <&syscrg JH7110_SYSCLK_I2C5_APB>;
|
|
clock-names = "ref";
|
|
resets = <&syscrg JH7110_SYSRST_I2C5_APB>;
|
|
interrupts = <50>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c6: i2c@12060000 {
|
|
compatible = "snps,designware-i2c";
|
|
reg = <0x0 0x12060000 0x0 0x10000>;
|
|
clocks = <&syscrg JH7110_SYSCLK_I2C6_APB>;
|
|
clock-names = "ref";
|
|
resets = <&syscrg JH7110_SYSRST_I2C6_APB>;
|
|
interrupts = <51>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi3: spi@12070000 {
|
|
compatible = "arm,pl022", "arm,primecell";
|
|
reg = <0x0 0x12070000 0x0 0x10000>;
|
|
clocks = <&syscrg JH7110_SYSCLK_SPI3_APB>,
|
|
<&syscrg JH7110_SYSCLK_SPI3_APB>;
|
|
clock-names = "sspclk", "apb_pclk";
|
|
resets = <&syscrg JH7110_SYSRST_SPI3_APB>;
|
|
interrupts = <52>;
|
|
arm,primecell-periphid = <0x00041022>;
|
|
num-cs = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi4: spi@12080000 {
|
|
compatible = "arm,pl022", "arm,primecell";
|
|
reg = <0x0 0x12080000 0x0 0x10000>;
|
|
clocks = <&syscrg JH7110_SYSCLK_SPI4_APB>,
|
|
<&syscrg JH7110_SYSCLK_SPI4_APB>;
|
|
clock-names = "sspclk", "apb_pclk";
|
|
resets = <&syscrg JH7110_SYSRST_SPI4_APB>;
|
|
interrupts = <53>;
|
|
arm,primecell-periphid = <0x00041022>;
|
|
num-cs = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi5: spi@12090000 {
|
|
compatible = "arm,pl022", "arm,primecell";
|
|
reg = <0x0 0x12090000 0x0 0x10000>;
|
|
clocks = <&syscrg JH7110_SYSCLK_SPI5_APB>,
|
|
<&syscrg JH7110_SYSCLK_SPI5_APB>;
|
|
clock-names = "sspclk", "apb_pclk";
|
|
resets = <&syscrg JH7110_SYSRST_SPI5_APB>;
|
|
interrupts = <54>;
|
|
arm,primecell-periphid = <0x00041022>;
|
|
num-cs = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi6: spi@120a0000 {
|
|
compatible = "arm,pl022", "arm,primecell";
|
|
reg = <0x0 0x120A0000 0x0 0x10000>;
|
|
clocks = <&syscrg JH7110_SYSCLK_SPI6_APB>,
|
|
<&syscrg JH7110_SYSCLK_SPI6_APB>;
|
|
clock-names = "sspclk", "apb_pclk";
|
|
resets = <&syscrg JH7110_SYSRST_SPI6_APB>;
|
|
interrupts = <55>;
|
|
arm,primecell-periphid = <0x00041022>;
|
|
num-cs = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2stx0: i2s@120b0000 {
|
|
compatible = "starfive,jh7110-i2stx0";
|
|
reg = <0x0 0x120b0000 0x0 0x1000>;
|
|
clocks = <&syscrg JH7110_SYSCLK_I2STX0_BCLK_MST>,
|
|
<&syscrg JH7110_SYSCLK_I2STX0_APB>,
|
|
<&syscrg JH7110_SYSCLK_MCLK>,
|
|
<&syscrg JH7110_SYSCLK_MCLK_INNER>,
|
|
<&mclk_ext>;
|
|
clock-names = "i2sclk", "apb", "mclk",
|
|
"mclk_inner","mclk_ext";
|
|
resets = <&syscrg JH7110_SYSRST_I2STX0_APB>,
|
|
<&syscrg JH7110_SYSRST_I2STX0_BCLK>;
|
|
dmas = <&dma 47>;
|
|
dma-names = "tx";
|
|
#sound-dai-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2stx1: i2s@120c0000 {
|
|
compatible = "starfive,jh7110-i2stx1";
|
|
reg = <0x0 0x120c0000 0x0 0x1000>;
|
|
clocks = <&syscrg JH7110_SYSCLK_I2STX1_BCLK_MST>,
|
|
<&syscrg JH7110_SYSCLK_I2STX1_APB>,
|
|
<&syscrg JH7110_SYSCLK_MCLK>,
|
|
<&syscrg JH7110_SYSCLK_MCLK_INNER>,
|
|
<&mclk_ext>,
|
|
<&syscrg JH7110_SYSCLK_I2STX1_BCLK>,
|
|
<&syscrg JH7110_SYSCLK_I2STX1_LRCK>,
|
|
<&i2stx_bclk_ext>,
|
|
<&i2stx_lrck_ext>;
|
|
clock-names = "i2sclk", "apb", "mclk",
|
|
"mclk_inner", "mclk_ext", "bclk",
|
|
"lrck", "bclk_ext", "lrck_ext";
|
|
resets = <&syscrg JH7110_SYSRST_I2STX1_APB>,
|
|
<&syscrg JH7110_SYSRST_I2STX1_BCLK>;
|
|
dmas = <&dma 48>;
|
|
dma-names = "tx";
|
|
#sound-dai-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm: pwm@120d0000 {
|
|
compatible = "starfive,jh7110-pwm", "opencores,pwm-v1";
|
|
reg = <0x0 0x120d0000 0x0 0x10000>;
|
|
clocks = <&syscrg JH7110_SYSCLK_PWM_APB>;
|
|
resets = <&syscrg JH7110_SYSRST_PWM_APB>;
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sfctemp: temperature-sensor@120e0000 {
|
|
compatible = "starfive,jh7110-temp";
|
|
reg = <0x0 0x120e0000 0x0 0x10000>;
|
|
clocks = <&syscrg JH7110_SYSCLK_TEMP_CORE>,
|
|
<&syscrg JH7110_SYSCLK_TEMP_APB>;
|
|
clock-names = "sense", "bus";
|
|
resets = <&syscrg JH7110_SYSRST_TEMP_CORE>,
|
|
<&syscrg JH7110_SYSRST_TEMP_APB>;
|
|
reset-names = "sense", "bus";
|
|
#thermal-sensor-cells = <0>;
|
|
};
|
|
|
|
qspi: spi@13010000 {
|
|
compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
|
|
reg = <0x0 0x13010000 0x0 0x10000>,
|
|
<0x0 0x21000000 0x0 0x400000>;
|
|
interrupts = <25>;
|
|
clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>,
|
|
<&syscrg JH7110_SYSCLK_QSPI_AHB>,
|
|
<&syscrg JH7110_SYSCLK_QSPI_APB>;
|
|
clock-names = "ref", "ahb", "apb";
|
|
resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
|
|
<&syscrg JH7110_SYSRST_QSPI_AHB>,
|
|
<&syscrg JH7110_SYSRST_QSPI_REF>;
|
|
reset-names = "qspi", "qspi-ocp", "rstc_ref";
|
|
cdns,fifo-depth = <256>;
|
|
cdns,fifo-width = <4>;
|
|
cdns,trigger-address = <0x0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
syscrg: clock-controller@13020000 {
|
|
compatible = "starfive,jh7110-syscrg";
|
|
reg = <0x0 0x13020000 0x0 0x10000>;
|
|
clocks = <&osc>, <&gmac1_rmii_refin>,
|
|
<&gmac1_rgmii_rxin>,
|
|
<&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
|
|
<&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
|
|
<&tdm_ext>, <&mclk_ext>,
|
|
<&pllclk JH7110_PLLCLK_PLL0_OUT>,
|
|
<&pllclk JH7110_PLLCLK_PLL1_OUT>,
|
|
<&pllclk JH7110_PLLCLK_PLL2_OUT>;
|
|
clock-names = "osc", "gmac1_rmii_refin",
|
|
"gmac1_rgmii_rxin",
|
|
"i2stx_bclk_ext", "i2stx_lrck_ext",
|
|
"i2srx_bclk_ext", "i2srx_lrck_ext",
|
|
"tdm_ext", "mclk_ext",
|
|
"pll0_out", "pll1_out", "pll2_out";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
sys_syscon: syscon@13030000 {
|
|
compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
|
|
reg = <0x0 0x13030000 0x0 0x1000>;
|
|
|
|
pllclk: clock-controller {
|
|
compatible = "starfive,jh7110-pll";
|
|
clocks = <&osc>;
|
|
#clock-cells = <1>;
|
|
};
|
|
};
|
|
|
|
sysgpio: pinctrl@13040000 {
|
|
compatible = "starfive,jh7110-sys-pinctrl";
|
|
reg = <0x0 0x13040000 0x0 0x10000>;
|
|
clocks = <&syscrg JH7110_SYSCLK_IOMUX_APB>;
|
|
resets = <&syscrg JH7110_SYSRST_IOMUX_APB>;
|
|
interrupts = <86>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
};
|
|
|
|
watchdog@13070000 {
|
|
compatible = "starfive,jh7110-wdt";
|
|
reg = <0x0 0x13070000 0x0 0x10000>;
|
|
clocks = <&syscrg JH7110_SYSCLK_WDT_APB>,
|
|
<&syscrg JH7110_SYSCLK_WDT_CORE>;
|
|
clock-names = "apb", "core";
|
|
resets = <&syscrg JH7110_SYSRST_WDT_APB>,
|
|
<&syscrg JH7110_SYSRST_WDT_CORE>;
|
|
};
|
|
|
|
crypto: crypto@16000000 {
|
|
compatible = "starfive,jh7110-crypto";
|
|
reg = <0x0 0x16000000 0x0 0x4000>;
|
|
clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>,
|
|
<&stgcrg JH7110_STGCLK_SEC_MISC_AHB>;
|
|
clock-names = "hclk", "ahb";
|
|
interrupts = <28>;
|
|
resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
|
|
dmas = <&sdma 1 2>, <&sdma 0 2>;
|
|
dma-names = "tx", "rx";
|
|
};
|
|
|
|
sdma: dma-controller@16008000 {
|
|
compatible = "arm,pl080", "arm,primecell";
|
|
arm,primecell-periphid = <0x00041080>;
|
|
reg = <0x0 0x16008000 0x0 0x4000>;
|
|
interrupts = <29>;
|
|
clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>;
|
|
clock-names = "apb_pclk";
|
|
resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
|
|
lli-bus-interface-ahb1;
|
|
mem-bus-interface-ahb1;
|
|
memcpy-burst-size = <256>;
|
|
memcpy-bus-width = <32>;
|
|
#dma-cells = <2>;
|
|
};
|
|
|
|
rng: rng@1600c000 {
|
|
compatible = "starfive,jh7110-trng";
|
|
reg = <0x0 0x1600C000 0x0 0x4000>;
|
|
clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>,
|
|
<&stgcrg JH7110_STGCLK_SEC_MISC_AHB>;
|
|
clock-names = "hclk", "ahb";
|
|
resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
|
|
interrupts = <30>;
|
|
};
|
|
|
|
mmc0: mmc@16010000 {
|
|
compatible = "starfive,jh7110-mmc";
|
|
reg = <0x0 0x16010000 0x0 0x10000>;
|
|
clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>,
|
|
<&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
|
|
clock-names = "biu","ciu";
|
|
resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>;
|
|
reset-names = "reset";
|
|
interrupts = <74>;
|
|
fifo-depth = <32>;
|
|
fifo-watermark-aligned;
|
|
data-addr = <0>;
|
|
starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mmc1: mmc@16020000 {
|
|
compatible = "starfive,jh7110-mmc";
|
|
reg = <0x0 0x16020000 0x0 0x10000>;
|
|
clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>,
|
|
<&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
|
|
clock-names = "biu","ciu";
|
|
resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>;
|
|
reset-names = "reset";
|
|
interrupts = <75>;
|
|
fifo-depth = <32>;
|
|
fifo-watermark-aligned;
|
|
data-addr = <0>;
|
|
starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gmac0: ethernet@16030000 {
|
|
compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
|
|
reg = <0x0 0x16030000 0x0 0x10000>;
|
|
clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>,
|
|
<&aoncrg JH7110_AONCLK_GMAC0_AHB>,
|
|
<&syscrg JH7110_SYSCLK_GMAC0_PTP>,
|
|
<&aoncrg JH7110_AONCLK_GMAC0_TX_INV>,
|
|
<&syscrg JH7110_SYSCLK_GMAC0_GTXC>;
|
|
clock-names = "stmmaceth", "pclk", "ptp_ref",
|
|
"tx", "gtx";
|
|
resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>,
|
|
<&aoncrg JH7110_AONRST_GMAC0_AHB>;
|
|
reset-names = "stmmaceth", "ahb";
|
|
interrupts = <7>, <6>, <5>;
|
|
interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
|
|
rx-fifo-depth = <2048>;
|
|
tx-fifo-depth = <2048>;
|
|
snps,multicast-filter-bins = <64>;
|
|
snps,perfect-filter-entries = <256>;
|
|
snps,fixed-burst;
|
|
snps,no-pbl-x8;
|
|
snps,force_thresh_dma_mode;
|
|
snps,axi-config = <&stmmac_axi_setup>;
|
|
snps,tso;
|
|
snps,txpbl = <16>;
|
|
snps,rxpbl = <16>;
|
|
starfive,syscon = <&aon_syscon 0xc 0x12>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gmac1: ethernet@16040000 {
|
|
compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
|
|
reg = <0x0 0x16040000 0x0 0x10000>;
|
|
clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>,
|
|
<&syscrg JH7110_SYSCLK_GMAC1_AHB>,
|
|
<&syscrg JH7110_SYSCLK_GMAC1_PTP>,
|
|
<&syscrg JH7110_SYSCLK_GMAC1_TX_INV>,
|
|
<&syscrg JH7110_SYSCLK_GMAC1_GTXC>;
|
|
clock-names = "stmmaceth", "pclk", "ptp_ref",
|
|
"tx", "gtx";
|
|
resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>,
|
|
<&syscrg JH7110_SYSRST_GMAC1_AHB>;
|
|
reset-names = "stmmaceth", "ahb";
|
|
interrupts = <78>, <77>, <76>;
|
|
interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
|
|
rx-fifo-depth = <2048>;
|
|
tx-fifo-depth = <2048>;
|
|
snps,multicast-filter-bins = <64>;
|
|
snps,perfect-filter-entries = <256>;
|
|
snps,fixed-burst;
|
|
snps,no-pbl-x8;
|
|
snps,force_thresh_dma_mode;
|
|
snps,axi-config = <&stmmac_axi_setup>;
|
|
snps,tso;
|
|
snps,txpbl = <16>;
|
|
snps,rxpbl = <16>;
|
|
starfive,syscon = <&sys_syscon 0x90 0x2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dma: dma-controller@16050000 {
|
|
compatible = "starfive,jh7110-axi-dma";
|
|
reg = <0x0 0x16050000 0x0 0x10000>;
|
|
clocks = <&stgcrg JH7110_STGCLK_DMA1P_AXI>,
|
|
<&stgcrg JH7110_STGCLK_DMA1P_AHB>;
|
|
clock-names = "core-clk", "cfgr-clk";
|
|
resets = <&stgcrg JH7110_STGRST_DMA1P_AXI>,
|
|
<&stgcrg JH7110_STGRST_DMA1P_AHB>;
|
|
interrupts = <73>;
|
|
#dma-cells = <1>;
|
|
dma-channels = <4>;
|
|
snps,dma-masters = <1>;
|
|
snps,data-width = <3>;
|
|
snps,block-size = <65536 65536 65536 65536>;
|
|
snps,priority = <0 1 2 3>;
|
|
snps,axi-max-burst-len = <16>;
|
|
};
|
|
|
|
aoncrg: clock-controller@17000000 {
|
|
compatible = "starfive,jh7110-aoncrg";
|
|
reg = <0x0 0x17000000 0x0 0x10000>;
|
|
clocks = <&osc>, <&gmac0_rmii_refin>,
|
|
<&gmac0_rgmii_rxin>,
|
|
<&syscrg JH7110_SYSCLK_STG_AXIAHB>,
|
|
<&syscrg JH7110_SYSCLK_APB_BUS>,
|
|
<&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>,
|
|
<&rtc_osc>;
|
|
clock-names = "osc", "gmac0_rmii_refin",
|
|
"gmac0_rgmii_rxin", "stg_axiahb",
|
|
"apb_bus", "gmac0_gtxclk",
|
|
"rtc_osc";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
aon_syscon: syscon@17010000 {
|
|
compatible = "starfive,jh7110-aon-syscon", "syscon";
|
|
reg = <0x0 0x17010000 0x0 0x1000>;
|
|
#power-domain-cells = <1>;
|
|
};
|
|
|
|
aongpio: pinctrl@17020000 {
|
|
compatible = "starfive,jh7110-aon-pinctrl";
|
|
reg = <0x0 0x17020000 0x0 0x10000>;
|
|
resets = <&aoncrg JH7110_AONRST_IOMUX>;
|
|
interrupts = <85>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
};
|
|
|
|
pwrc: power-controller@17030000 {
|
|
compatible = "starfive,jh7110-pmu";
|
|
reg = <0x0 0x17030000 0x0 0x10000>;
|
|
interrupts = <111>;
|
|
#power-domain-cells = <1>;
|
|
};
|
|
|
|
csi2rx: csi@19800000 {
|
|
compatible = "starfive,jh7110-csi2rx", "cdns,csi2rx";
|
|
reg = <0x0 0x19800000 0x0 0x10000>;
|
|
clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>,
|
|
<&ispcrg JH7110_ISPCLK_VIN_APB>,
|
|
<&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF0>,
|
|
<&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF1>,
|
|
<&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF2>,
|
|
<&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF3>;
|
|
clock-names = "sys_clk", "p_clk",
|
|
"pixel_if0_clk", "pixel_if1_clk",
|
|
"pixel_if2_clk", "pixel_if3_clk";
|
|
resets = <&ispcrg JH7110_ISPRST_VIN_SYS>,
|
|
<&ispcrg JH7110_ISPRST_VIN_APB>,
|
|
<&ispcrg JH7110_ISPRST_VIN_PIXEL_IF0>,
|
|
<&ispcrg JH7110_ISPRST_VIN_PIXEL_IF1>,
|
|
<&ispcrg JH7110_ISPRST_VIN_PIXEL_IF2>,
|
|
<&ispcrg JH7110_ISPRST_VIN_PIXEL_IF3>;
|
|
reset-names = "sys", "reg_bank",
|
|
"pixel_if0", "pixel_if1",
|
|
"pixel_if2", "pixel_if3";
|
|
phys = <&csi_phy>;
|
|
phy-names = "dphy";
|
|
status = "disabled";
|
|
};
|
|
|
|
ispcrg: clock-controller@19810000 {
|
|
compatible = "starfive,jh7110-ispcrg";
|
|
reg = <0x0 0x19810000 0x0 0x10000>;
|
|
clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,
|
|
<&syscrg JH7110_SYSCLK_ISP_TOP_AXI>,
|
|
<&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>,
|
|
<&dvp_clk>;
|
|
clock-names = "isp_top_core", "isp_top_axi",
|
|
"noc_bus_isp_axi", "dvp_clk";
|
|
resets = <&syscrg JH7110_SYSRST_ISP_TOP>,
|
|
<&syscrg JH7110_SYSRST_ISP_TOP_AXI>,
|
|
<&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
power-domains = <&pwrc JH7110_PD_ISP>;
|
|
};
|
|
|
|
csi_phy: phy@19820000 {
|
|
compatible = "starfive,jh7110-dphy-rx";
|
|
reg = <0x0 0x19820000 0x0 0x10000>;
|
|
clocks = <&ispcrg JH7110_ISPCLK_M31DPHY_CFG_IN>,
|
|
<&ispcrg JH7110_ISPCLK_M31DPHY_REF_IN>,
|
|
<&ispcrg JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0>;
|
|
clock-names = "cfg", "ref", "tx";
|
|
resets = <&ispcrg JH7110_ISPRST_M31DPHY_HW>,
|
|
<&ispcrg JH7110_ISPRST_M31DPHY_B09_AON>;
|
|
power-domains = <&aon_syscon JH7110_AON_PD_DPHY_RX>;
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
camss: isp@19840000 {
|
|
compatible = "starfive,jh7110-camss";
|
|
reg = <0x0 0x19840000 0x0 0x10000>,
|
|
<0x0 0x19870000 0x0 0x30000>;
|
|
reg-names = "syscon", "isp";
|
|
clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>,
|
|
<&ispcrg JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C>,
|
|
<&ispcrg JH7110_ISPCLK_DVP_INV>,
|
|
<&ispcrg JH7110_ISPCLK_VIN_P_AXI_WR>,
|
|
<&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>,
|
|
<&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,
|
|
<&syscrg JH7110_SYSCLK_ISP_TOP_AXI>;
|
|
clock-names = "apb_func", "wrapper_clk_c", "dvp_inv",
|
|
"axiwr", "mipi_rx0_pxl", "ispcore_2x",
|
|
"isp_axi";
|
|
resets = <&ispcrg JH7110_ISPRST_ISPV2_TOP_WRAPPER_P>,
|
|
<&ispcrg JH7110_ISPRST_ISPV2_TOP_WRAPPER_C>,
|
|
<&ispcrg JH7110_ISPRST_VIN_P_AXI_RD>,
|
|
<&ispcrg JH7110_ISPRST_VIN_P_AXI_WR>,
|
|
<&syscrg JH7110_SYSRST_ISP_TOP>,
|
|
<&syscrg JH7110_SYSRST_ISP_TOP_AXI>;
|
|
reset-names = "wrapper_p", "wrapper_c", "axird",
|
|
"axiwr", "isp_top_n", "isp_top_axi";
|
|
power-domains = <&pwrc JH7110_PD_ISP>;
|
|
interrupts = <92>, <87>, <90>, <88>;
|
|
status = "disabled";
|
|
};
|
|
|
|
voutcrg: clock-controller@295c0000 {
|
|
compatible = "starfive,jh7110-voutcrg";
|
|
reg = <0x0 0x295c0000 0x0 0x10000>;
|
|
clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>,
|
|
<&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>,
|
|
<&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>,
|
|
<&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,
|
|
<&syscrg JH7110_SYSCLK_I2STX0_BCLK>,
|
|
<&hdmitx0_pixelclk>;
|
|
clock-names = "vout_src", "vout_top_ahb",
|
|
"vout_top_axi", "vout_top_hdmitx0_mclk",
|
|
"i2stx0_bclk", "hdmitx0_pixelclk";
|
|
resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
power-domains = <&pwrc JH7110_PD_VOUT>;
|
|
};
|
|
|
|
pcie0: pcie@940000000 {
|
|
compatible = "starfive,jh7110-pcie";
|
|
reg = <0x9 0x40000000 0x0 0x1000000>,
|
|
<0x0 0x2b000000 0x0 0x100000>;
|
|
reg-names = "cfg", "apb";
|
|
linux,pci-domain = <0>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
#interrupt-cells = <1>;
|
|
ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>,
|
|
<0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
|
|
interrupts = <56>;
|
|
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
|
interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>,
|
|
<0x0 0x0 0x0 0x2 &pcie_intc0 0x2>,
|
|
<0x0 0x0 0x0 0x3 &pcie_intc0 0x3>,
|
|
<0x0 0x0 0x0 0x4 &pcie_intc0 0x4>;
|
|
msi-controller;
|
|
device_type = "pci";
|
|
starfive,stg-syscon = <&stg_syscon>;
|
|
bus-range = <0x0 0xff>;
|
|
clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
|
|
<&stgcrg JH7110_STGCLK_PCIE0_TL>,
|
|
<&stgcrg JH7110_STGCLK_PCIE0_AXI_MST0>,
|
|
<&stgcrg JH7110_STGCLK_PCIE0_APB>;
|
|
clock-names = "noc", "tl", "axi_mst0", "apb";
|
|
resets = <&stgcrg JH7110_STGRST_PCIE0_AXI_MST0>,
|
|
<&stgcrg JH7110_STGRST_PCIE0_AXI_SLV0>,
|
|
<&stgcrg JH7110_STGRST_PCIE0_AXI_SLV>,
|
|
<&stgcrg JH7110_STGRST_PCIE0_BRG>,
|
|
<&stgcrg JH7110_STGRST_PCIE0_CORE>,
|
|
<&stgcrg JH7110_STGRST_PCIE0_APB>;
|
|
reset-names = "mst0", "slv0", "slv", "brg",
|
|
"core", "apb";
|
|
status = "disabled";
|
|
|
|
pcie_intc0: interrupt-controller {
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-controller;
|
|
};
|
|
};
|
|
|
|
pcie1: pcie@9c0000000 {
|
|
compatible = "starfive,jh7110-pcie";
|
|
reg = <0x9 0xc0000000 0x0 0x1000000>,
|
|
<0x0 0x2c000000 0x0 0x100000>;
|
|
reg-names = "cfg", "apb";
|
|
linux,pci-domain = <1>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
#interrupt-cells = <1>;
|
|
ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>,
|
|
<0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
|
|
interrupts = <57>;
|
|
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
|
interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc1 0x1>,
|
|
<0x0 0x0 0x0 0x2 &pcie_intc1 0x2>,
|
|
<0x0 0x0 0x0 0x3 &pcie_intc1 0x3>,
|
|
<0x0 0x0 0x0 0x4 &pcie_intc1 0x4>;
|
|
msi-controller;
|
|
device_type = "pci";
|
|
starfive,stg-syscon = <&stg_syscon>;
|
|
bus-range = <0x0 0xff>;
|
|
clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
|
|
<&stgcrg JH7110_STGCLK_PCIE1_TL>,
|
|
<&stgcrg JH7110_STGCLK_PCIE1_AXI_MST0>,
|
|
<&stgcrg JH7110_STGCLK_PCIE1_APB>;
|
|
clock-names = "noc", "tl", "axi_mst0", "apb";
|
|
resets = <&stgcrg JH7110_STGRST_PCIE1_AXI_MST0>,
|
|
<&stgcrg JH7110_STGRST_PCIE1_AXI_SLV0>,
|
|
<&stgcrg JH7110_STGRST_PCIE1_AXI_SLV>,
|
|
<&stgcrg JH7110_STGRST_PCIE1_BRG>,
|
|
<&stgcrg JH7110_STGRST_PCIE1_CORE>,
|
|
<&stgcrg JH7110_STGRST_PCIE1_APB>;
|
|
reset-names = "mst0", "slv0", "slv", "brg",
|
|
"core", "apb";
|
|
status = "disabled";
|
|
|
|
pcie_intc1: interrupt-controller {
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-controller;
|
|
};
|
|
};
|
|
};
|
|
};
|