mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-01 06:39:05 +00:00
3f41368fbf
Add an initial devicetree for the BeagleV Fire. This devicetree differs from that in the BeagleBoard BSP as it has a different memory configuration, however it will boot on the same FPGA images. PCI is disabled for now, as the Linux PCI driver (and the binding) assume which root port instance is in use. This will need to be fixed before PCI can be enabled. Link: https://www.beagleboard.org/boards/beaglev-fire Co-developed-by: Jamie Gibbons <jamie.gibbons@microchip.com> Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
83 lines
2.5 KiB
Plaintext
83 lines
2.5 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/ {
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fabric_clk3: fabric-clk3 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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};
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fabric_clk1: fabric-clk1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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};
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fabric-bus@40000000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>, /* FIC3-FAB */
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<0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>, /* FIC0, LO */
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<0x0 0xe0000000 0x0 0xe0000000 0x0 0x20000000>, /* FIC1, LO */
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<0x20 0x0 0x20 0x0 0x10 0x0>, /* FIC0,HI */
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<0x30 0x0 0x30 0x0 0x10 0x0>; /* FIC1,HI */
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cape_gpios_p8: gpio@41100000 {
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compatible = "microchip,coregpio-rtl-v3";
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reg = <0x0 0x41100000 0x0 0x1000>;
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clocks = <&fabric_clk3>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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gpio-line-names = "P8_PIN31", "P8_PIN32", "P8_PIN33", "P8_PIN34",
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"P8_PIN35", "P8_PIN36", "P8_PIN37", "P8_PIN38",
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"P8_PIN39", "P8_PIN40", "P8_PIN41", "P8_PIN42",
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"P8_PIN43", "P8_PIN44", "P8_PIN45", "P8_PIN46";
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};
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cape_gpios_p9: gpio@41200000 {
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compatible = "microchip,coregpio-rtl-v3";
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reg = <0x0 0x41200000 0x0 0x1000>;
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clocks = <&fabric_clk3>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <20>;
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gpio-line-names = "P9_PIN11", "P9_PIN12", "P9_PIN13", "P9_PIN14",
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"P9_PIN15", "P9_PIN16", "P9_PIN17", "P9_PIN18",
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"P9_PIN21", "P9_PIN22", "P9_PIN23", "P9_PIN24",
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"P9_PIN25", "P9_PIN26", "P9_PIN27", "P9_PIN28",
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"P9_PIN29", "P9_PIN31", "P9_PIN41", "P9_PIN42";
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};
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hsi_gpios: gpio@44000000 {
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compatible = "microchip,coregpio-rtl-v3";
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reg = <0x0 0x44000000 0x0 0x1000>;
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clocks = <&fabric_clk3>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <20>;
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gpio-line-names = "B0_HSIO70N", "B0_HSIO71N", "B0_HSIO83N",
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"B0_HSIO73N_C2P_CLKN", "B0_HSIO70P", "B0_HSIO71P",
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"B0_HSIO83P", "B0_HSIO73N_C2P_CLKP", "XCVR1_RX_VALID",
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"XCVR1_LOCK", "XCVR1_ERROR", "XCVR2_RX_VALID",
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"XCVR2_LOCK", "XCVR2_ERROR", "XCVR3_RX_VALID",
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"XCVR3_LOCK", "XCVR3_ERROR", "XCVR_0B_REF_CLK_PLL_LOCK",
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"XCVR_0C_REF_CLK_PLL_LOCK", "B0_HSIO81N";
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};
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};
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refclk_ccc: cccrefclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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};
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&ccc_nw {
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clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
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<&refclk_ccc>, <&refclk_ccc>;
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clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",
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"dll0_ref", "dll1_ref";
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status = "okay";
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};
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