mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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2d147d77ae
Add SiFive vendor extension support to the kernel with the target of "xsfvqmaccdod" and "xsfvqmaccqoq". Signed-off-by: Cyan Yang <cyan.yang@sifive.com> Link: https://lore.kernel.org/r/20250418053239.4351-3-cyan.yang@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
59 lines
1.6 KiB
Plaintext
59 lines
1.6 KiB
Plaintext
menu "Vendor extensions"
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config RISCV_ISA_VENDOR_EXT
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bool
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menu "Andes"
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config RISCV_ISA_VENDOR_EXT_ANDES
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bool "Andes vendor extension support"
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select RISCV_ISA_VENDOR_EXT
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default y
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help
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Say N here if you want to disable all Andes vendor extension
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support. This will cause any Andes vendor extensions that are
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requested by hardware probing to be ignored.
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If you don't know what to do here, say Y.
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endmenu
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menu "SiFive"
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config RISCV_ISA_VENDOR_EXT_SIFIVE
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bool "SiFive vendor extension support"
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select RISCV_ISA_VENDOR_EXT
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default y
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help
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Say N here if you want to disable all SiFive vendor extension
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support. This will cause any SiFive vendor extensions that are
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requested by hardware probing to be ignored.
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If you don't know what to do here, say Y.
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endmenu
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menu "T-Head"
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config RISCV_ISA_VENDOR_EXT_THEAD
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bool "T-Head vendor extension support"
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select RISCV_ISA_VENDOR_EXT
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default y
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help
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Say N here to disable detection of and support for all T-Head vendor
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extensions. Without this option enabled, T-Head vendor extensions will
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not be detected at boot and their presence not reported to userspace.
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If you don't know what to do here, say Y.
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config RISCV_ISA_XTHEADVECTOR
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bool "xtheadvector extension support"
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depends on RISCV_ISA_VENDOR_EXT_THEAD
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depends on RISCV_ISA_V
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depends on FPU
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default y
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help
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Say N here if you want to disable all xtheadvector related procedures
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in the kernel. This will disable vector for any T-Head board that
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contains xtheadvector rather than the standard vector.
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If you don't know what to do here, say Y.
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endmenu
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endmenu
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