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7c44202e36
e500 supports many page sizes among which the following size are implemented in the kernel at the time being: 4M, 16M, 64M, 256M, 1G. On e500, TLB miss for hugepages is exclusively handled by SW even on e6500 which has HW assistance for 4k pages, so there are no constraints like on the 8xx. On e500/32, all are at PGD/PMD level and can be handled as cont-PMD. On e500/64, smaller ones are on PMD while bigger ones are on PUD. Again, they can easily be handled as cont-PMD and cont-PUD instead of hugepd. On e500/32, use the pagesize bits in PTE to know if it is a PMD or a leaf entry. This works because the pagesize bits are in the last 12 bits and page tables are 4k aligned. On e500/64, use highest bit which is always 1 on PxD (Because PxD contains virtual address of a kernel memory) and always 0 on PTEs because not all bits of RPN are used/possible. Link: https://lkml.kernel.org/r/dd085987816ed2a0c70adb7e34966cb833fc03e1.1719928057.git.christophe.leroy@csgroup.eu Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Cc: Jason Gunthorpe <jgg@nvidia.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Nicholas Piggin <npiggin@gmail.com> Cc: Oscar Salvador <osalvador@suse.de> Cc: Peter Xu <peterx@redhat.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
141 lines
3.9 KiB
C
141 lines
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_POWERPC_NOHASH_PTE_E500_H
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#define _ASM_POWERPC_NOHASH_PTE_E500_H
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#ifdef __KERNEL__
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/* PTE bit definitions for processors compliant to the Book3E
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* architecture 2.06 or later. The position of the PTE bits
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* matches the HW definition of the optional Embedded Page Table
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* category.
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*/
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/* Architected bits */
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#define _PAGE_PRESENT 0x000001 /* software: pte contains a translation */
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#define _PAGE_SW1 0x000002
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#define _PAGE_BAP_SR 0x000004
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#define _PAGE_BAP_UR 0x000008
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#define _PAGE_BAP_SW 0x000010
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#define _PAGE_BAP_UW 0x000020
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#define _PAGE_BAP_SX 0x000040
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#define _PAGE_BAP_UX 0x000080
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#define _PAGE_PSIZE_MSK 0x000f00
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#define _PAGE_TSIZE_4K 0x000100
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#define _PAGE_DIRTY 0x001000 /* C: page changed */
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#define _PAGE_SW0 0x002000
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#define _PAGE_U3 0x004000
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#define _PAGE_U2 0x008000
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#define _PAGE_U1 0x010000
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#define _PAGE_U0 0x020000
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#define _PAGE_ACCESSED 0x040000
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#define _PAGE_ENDIAN 0x080000
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#define _PAGE_GUARDED 0x100000
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#define _PAGE_COHERENT 0x200000 /* M: enforce memory coherence */
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#define _PAGE_NO_CACHE 0x400000 /* I: cache inhibit */
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#define _PAGE_WRITETHRU 0x800000 /* W: cache write-through */
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#define _PAGE_PSIZE_SHIFT 7
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#define _PAGE_PSIZE_SHIFT_OFFSET 10
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/* "Higher level" linux bit combinations */
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#define _PAGE_EXEC (_PAGE_BAP_SX | _PAGE_BAP_UX) /* .. and was cache cleaned */
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#define _PAGE_READ (_PAGE_BAP_SR | _PAGE_BAP_UR) /* User read permission */
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#define _PAGE_WRITE (_PAGE_BAP_SW | _PAGE_BAP_UW) /* User write permission */
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#define _PAGE_KERNEL_RW (_PAGE_BAP_SW | _PAGE_BAP_SR | _PAGE_DIRTY)
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#define _PAGE_KERNEL_RO (_PAGE_BAP_SR)
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#define _PAGE_KERNEL_RWX (_PAGE_BAP_SW | _PAGE_BAP_SR | _PAGE_DIRTY | _PAGE_BAP_SX)
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#define _PAGE_KERNEL_ROX (_PAGE_BAP_SR | _PAGE_BAP_SX)
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#define _PAGE_NA 0
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#define _PAGE_NAX _PAGE_BAP_UX
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#define _PAGE_RO _PAGE_READ
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#define _PAGE_ROX (_PAGE_READ | _PAGE_BAP_UX)
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#define _PAGE_RW (_PAGE_READ | _PAGE_WRITE)
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#define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_BAP_UX)
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#define _PAGE_SPECIAL _PAGE_SW0
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#define PTE_RPN_SHIFT (24)
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#define PTE_WIMGE_SHIFT (19)
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#define PTE_BAP_SHIFT (2)
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/* On 32-bit, we never clear the top part of the PTE */
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#ifdef CONFIG_PPC32
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#define _PTE_NONE_MASK 0xffffffff00000000ULL
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#define _PMD_PRESENT 0
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#define _PMD_PRESENT_MASK (PAGE_MASK)
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#define _PMD_BAD (~PAGE_MASK)
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#define _PMD_USER 0
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#else
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#define _PTE_NONE_MASK 0
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#endif
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/*
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* We define 2 sets of base prot bits, one for basic pages (ie,
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* cacheable kernel and user pages) and one for non cacheable
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* pages. We always set _PAGE_COHERENT when SMP is enabled or
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* the processor might need it for DMA coherency.
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*/
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#define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_TSIZE_4K)
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#if defined(CONFIG_SMP)
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#define _PAGE_BASE (_PAGE_BASE_NC | _PAGE_COHERENT)
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#else
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#define _PAGE_BASE (_PAGE_BASE_NC)
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#endif
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#include <asm/pgtable-masks.h>
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#ifndef __ASSEMBLY__
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static inline pte_t pte_mkexec(pte_t pte)
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{
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return __pte((pte_val(pte) & ~_PAGE_BAP_SX) | _PAGE_BAP_UX);
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}
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#define pte_mkexec pte_mkexec
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static inline unsigned long pte_huge_size(pte_t pte)
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{
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pte_basic_t val = pte_val(pte);
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return 1UL << (((val & _PAGE_PSIZE_MSK) >> _PAGE_PSIZE_SHIFT) + _PAGE_PSIZE_SHIFT_OFFSET);
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}
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#define pte_huge_size pte_huge_size
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static inline int pmd_leaf(pmd_t pmd)
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{
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if (IS_ENABLED(CONFIG_PPC64))
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return (long)pmd_val(pmd) > 0;
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else
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return pmd_val(pmd) & _PAGE_PSIZE_MSK;
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}
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#define pmd_leaf pmd_leaf
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static inline unsigned long pmd_leaf_size(pmd_t pmd)
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{
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return pte_huge_size(__pte(pmd_val(pmd)));
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}
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#define pmd_leaf_size pmd_leaf_size
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#ifdef CONFIG_PPC64
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static inline int pud_leaf(pud_t pud)
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{
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if (IS_ENABLED(CONFIG_PPC64))
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return (long)pud_val(pud) > 0;
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else
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return pud_val(pud) & _PAGE_PSIZE_MSK;
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}
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#define pud_leaf pud_leaf
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static inline unsigned long pud_leaf_size(pud_t pud)
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{
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return pte_huge_size(__pte(pud_val(pud)));
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}
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#define pud_leaf_size pud_leaf_size
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_NOHASH_PTE_E500_H */
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