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0c4a6e79ef
According to the OpenRISC architecture manual, the dcache and icache may not be present. When these caches are present, the invalidate and flush registers may be absent. The current implementation does not perform checks to verify their presence before utilizing cache registers, or invalidating and flushing cache blocks. Introduce new functions to detect the presence of cache components and related special-purpose registers. There are a few places where a range of addresses have to be flushed or invalidated and the implementation is duplicated. Introduce new utility functions and macros that generalize this implementation and reduce duplication. Signed-off-by: Sahil Siddiq <sahilcdq0@gmail.com> Signed-off-by: Stafford Horne <shorne@gmail.com>
97 lines
3.1 KiB
C
97 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* OpenRISC Linux
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*
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* Linux architectural port borrowing liberally from similar works of
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* others. All original copyrights apply as per the original source
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* declaration.
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*
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* OpenRISC implementation:
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* Copyright (C) Jan Henrik Weinstock <jan.weinstock@rwth-aachen.de>
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* et al.
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*/
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#ifndef __ASM_CACHEFLUSH_H
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#define __ASM_CACHEFLUSH_H
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#include <linux/mm.h>
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/*
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* Helper function for flushing or invalidating entire pages from data
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* and instruction caches. SMP needs a little extra work, since we need
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* to flush the pages on all cpus.
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*/
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extern void local_dcache_page_flush(struct page *page);
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extern void local_icache_page_inv(struct page *page);
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extern void local_dcache_range_flush(unsigned long start, unsigned long end);
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extern void local_dcache_range_inv(unsigned long start, unsigned long end);
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extern void local_icache_range_inv(unsigned long start, unsigned long end);
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/*
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* Data cache flushing always happen on the local cpu. Instruction cache
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* invalidations need to be broadcasted to all other cpu in the system in
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* case of SMP configurations.
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*/
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#ifndef CONFIG_SMP
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#define dcache_page_flush(page) local_dcache_page_flush(page)
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#define icache_page_inv(page) local_icache_page_inv(page)
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#else /* CONFIG_SMP */
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#define dcache_page_flush(page) local_dcache_page_flush(page)
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#define icache_page_inv(page) smp_icache_page_inv(page)
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extern void smp_icache_page_inv(struct page *page);
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#endif /* CONFIG_SMP */
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/*
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* Even if the actual block size is larger than L1_CACHE_BYTES, paddr
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* can be incremented by L1_CACHE_BYTES. When paddr is written to the
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* invalidate register, the entire cache line encompassing this address
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* is invalidated. Each subsequent reference to the same cache line will
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* not affect the invalidation process.
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*/
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#define local_dcache_block_flush(addr) \
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local_dcache_range_flush(addr, addr + L1_CACHE_BYTES)
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#define local_dcache_block_inv(addr) \
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local_dcache_range_inv(addr, addr + L1_CACHE_BYTES)
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#define local_icache_block_inv(addr) \
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local_icache_range_inv(addr, addr + L1_CACHE_BYTES)
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/*
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* Synchronizes caches. Whenever a cpu writes executable code to memory, this
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* should be called to make sure the processor sees the newly written code.
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*/
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static inline void sync_icache_dcache(struct page *page)
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{
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if (!IS_ENABLED(CONFIG_DCACHE_WRITETHROUGH))
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dcache_page_flush(page);
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icache_page_inv(page);
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}
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/*
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* Pages with this bit set need not be flushed/invalidated, since
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* they have not changed since last flush. New pages start with
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* PG_arch_1 not set and are therefore dirty by default.
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*/
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#define PG_dc_clean PG_arch_1
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static inline void flush_dcache_folio(struct folio *folio)
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{
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clear_bit(PG_dc_clean, &folio->flags);
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}
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#define flush_dcache_folio flush_dcache_folio
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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static inline void flush_dcache_page(struct page *page)
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{
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flush_dcache_folio(page_folio(page));
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}
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#define flush_icache_user_page(vma, page, addr, len) \
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do { \
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if (vma->vm_flags & VM_EXEC) \
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sync_icache_dcache(page); \
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} while (0)
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#include <asm-generic/cacheflush.h>
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#endif /* __ASM_CACHEFLUSH_H */
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