linux-loongson/arch/mips/boot/dts/realtek/cameo-rtl9302c-2x-rtl8224-2xge.dts

// SPDX-License-Identifier: GPL-2.0-or-later
/dts-v1/;

#include "rtl9302c.dtsi"

#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	compatible = "cameo,rtl9302c-2x-rtl8224-2xge", "realtek,rtl9302-soc";
	model = "RTL9302C Development Board";

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x8000000>;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};
};

&uart0 {
	status = "okay";
};

&spi0 {
	status = "okay";
	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <10000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "LOADER";
				reg = <0x0 0xe0000>;
				read-only;
			};
			partition@e0000 {
				label = "BDINFO";
				reg = <0xe0000 0x10000>;
			};
			partition@f0000 {
				label = "SYSINFO";
				reg = <0xf0000 0x10000>;
				read-only;
			};
			partition@100000 {
				label = "JFFS2 CFG";
				reg = <0x100000 0x100000>;
			};
			partition@200000 {
				label = "JFFS2 LOG";
				reg = <0x200000 0x100000>;
			};
			partition@300000 {
				label = "RUNTIME";
				reg = <0x300000 0xe80000>;
			};
			partition@1180000 {
				label = "RUNTIME2";
				reg = <0x1180000 0xe80000>;
			};
		};
	};
};

&mdio0 {
	/* External RTL8224 */
	phy0: ethernet-phy@0 {
		reg = <0>;
		compatible = "ethernet-phy-ieee802.3-c45";
	};
	phy1: ethernet-phy@1 {
		reg = <1>;
		compatible = "ethernet-phy-ieee802.3-c45";
	};
	phy2: ethernet-phy@2 {
		reg = <2>;
		compatible = "ethernet-phy-ieee802.3-c45";
	};
	phy3: ethernet-phy@3 {
		reg = <3>;
		compatible = "ethernet-phy-ieee802.3-c45";
	};
};

&mdio1 {
	/* External RTL8224 */
	phy4: ethernet-phy@0 {
		reg = <0>;
		compatible = "ethernet-phy-ieee802.3-c45";
	};
	phy5: ethernet-phy@1 {
		reg = <1>;
		compatible = "ethernet-phy-ieee802.3-c45";
	};
	phy6: ethernet-phy@2 {
		reg = <2>;
		compatible = "ethernet-phy-ieee802.3-c45";
	};
	phy7: ethernet-phy@3 {
		reg = <3>;
		compatible = "ethernet-phy-ieee802.3-c45";
	};
};

&switch0 {
	ethernet-ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
			reg = <0>;
			phy-handle = <&phy0>;
			phy-mode = "usxgmii";
		};
		port@1 {
			reg = <1>;
			phy-handle = <&phy1>;
			phy-mode = "usxgmii";
		};
		port@2 {
			reg = <2>;
			phy-handle = <&phy2>;
			phy-mode = "usxgmii";
		};
		port@3 {
			reg = <3>;
			phy-handle = <&phy3>;
			phy-mode = "usxgmii";
		};
		port@16 {
			reg = <16>;
			phy-handle = <&phy4>;
			phy-mode = "usxgmii";
		};
		port@17 {
			reg = <17>;
			phy-handle = <&phy5>;
			phy-mode = "usxgmii";
		};
		port@18 {
			reg = <18>;
			phy-handle = <&phy6>;
			phy-mode = "usxgmii";
		};
		port@19 {
			reg = <19>;
			phy-handle = <&phy7>;
			phy-mode = "usxgmii";
		};
		port@24{
			reg = <24>;
			phy-mode = "10gbase-r";
		};
		port@25{
			reg = <25>;
			phy-mode = "10gbase-r";
		};
	};
};