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adc4cefae9
To inject the error using the tmr inject IP reset vectors need to be placed in lmb(bram) due to the limitation in HW when this code runs out of DDR. Below code adds the error inject code to the .init.ivt section to copy it in machine_early_init to lmb/Bram location. C_BASE_VECTORS which allow moving reset vectors out of 0 location is not currently supported by Microblaze architecture, that's why all the time reset vectors with injection code is all the time copied to address 0. As of now getting this functionality working CPU switches to real mode and simply jumps to bram, which causes triggering of fault which continues to call_xmb_manager_break break handler which will at the end calls the error count callback function and performs recovery. Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com> Link: https://lore.kernel.org/r/20220627064024.771037-4-appana.durga.rao@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
30 lines
859 B
C
30 lines
859 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2022 Xilinx, Inc.
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*/
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#ifndef _XILINX_MB_MANAGER_H
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#define _XILINX_MB_MANAGER_H
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# ifndef __ASSEMBLY__
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#include <linux/of_address.h>
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/*
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* When the break vector gets asserted because of error injection, the break
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* signal must be blocked before exiting from the break handler, Below api
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* updates the manager address and control register and error counter callback
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* arguments, which will be used by the break handler to block the break and
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* call the callback function.
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*/
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void xmb_manager_register(uintptr_t phys_baseaddr, u32 cr_val,
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void (*callback)(void *data),
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void *priv, void (*reset_callback)(void *data));
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asmlinkage void xmb_inject_err(void);
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# endif /* __ASSEMBLY__ */
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/* Error injection offset */
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#define XMB_INJECT_ERR_OFFSET 0x200
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#endif /* _XILINX_MB_MANAGER_H */
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