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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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41604bfdc9
This patch removes support for the Xilinx PCI host bridge IPcore. Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com> Link: https://lore.kernel.org/r/20221025065214.4663-13-thippeswamy.havalige@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
50 lines
1.0 KiB
C
50 lines
1.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef _ASM_MICROBLAZE_PCI_BRIDGE_H
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#define _ASM_MICROBLAZE_PCI_BRIDGE_H
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#ifdef __KERNEL__
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/*
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*/
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#include <linux/pci.h>
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#include <linux/list.h>
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#include <linux/ioport.h>
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struct device_node;
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#ifdef CONFIG_PCI
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extern struct list_head hose_list;
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extern int pcibios_vaddr_is_ioport(void __iomem *address);
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#else
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static inline int pcibios_vaddr_is_ioport(void __iomem *address)
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{
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return 0;
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}
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#endif
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/*
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* Structure of a PCI controller (host bridge)
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*/
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struct pci_controller {
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struct pci_bus *bus;
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struct list_head list_node;
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void __iomem *io_base_virt;
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/* Currently, we limit ourselves to 1 IO range and 3 mem
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* ranges since the common pci_bus structure can't handle more
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*/
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struct resource io_resource;
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};
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#ifdef CONFIG_PCI
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static inline int isa_vaddr_is_ioport(void __iomem *address)
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{
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/* No specific ISA handling on ppc32 at this stage, it
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* all goes through PCI
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*/
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return 0;
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}
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#endif /* CONFIG_PCI */
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#endif /* __KERNEL__ */
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#endif /* _ASM_MICROBLAZE_PCI_BRIDGE_H */
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