mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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8a20030038
Sparse reports
net/ipv4/inet_diag.c:1511:17: sparse: sparse: Using plain integer as NULL pointer
Due to this code calling cmpxchg on a non-integer type
struct inet_diag_handler *
return !cmpxchg((const struct inet_diag_handler**)&inet_diag_table[type],
NULL, h) ? 0 : -EEXIST;
While hexagon's cmpxchg assigns an integer value to a variable of this
type.
__typeof__(*(ptr)) __oldval = 0;
Update this assignment to cast 0 to the correct type.
The original issue is easily reproduced at head with the below block,
and is absent after this change.
make LLVM=1 ARCH=hexagon defconfig
make C=1 LLVM=1 ARCH=hexagon net/ipv4/inet_diag.o
Fixes: 99a70aa051 ("Hexagon: Add processor and system headers")
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202411091538.PGSTqUBi-lkp@intel.com/
Signed-off-by: Willem de Bruijn <willemb@google.com>
Tested-by: Christian Gmeiner <cgmeiner@igalia.com>
Link: https://lore.kernel.org/r/20241203221736.282020-1-willemdebruijn.kernel@gmail.com
Signed-off-by: Brian Cain <bcain@quicinc.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
76 lines
2.0 KiB
C
76 lines
2.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* xchg/cmpxchg operations for the Hexagon architecture
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*
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* Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
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*/
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#ifndef _ASM_CMPXCHG_H
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#define _ASM_CMPXCHG_H
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/*
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* __arch_xchg - atomically exchange a register and a memory location
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* @x: value to swap
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* @ptr: pointer to memory
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* @size: size of the value
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*
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* Only 4 bytes supported currently.
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*
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* Note: there was an errata for V2 about .new's and memw_locked.
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*
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*/
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static inline unsigned long
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__arch_xchg(unsigned long x, volatile void *ptr, int size)
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{
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unsigned long retval;
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/* Can't seem to use printk or panic here, so just stop */
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if (size != 4) do { asm volatile("brkpt;\n"); } while (1);
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__asm__ __volatile__ (
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"1: %0 = memw_locked(%1);\n" /* load into retval */
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" memw_locked(%1,P0) = %2;\n" /* store into memory */
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" if (!P0) jump 1b;\n"
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: "=&r" (retval)
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: "r" (ptr), "r" (x)
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: "memory", "p0"
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);
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return retval;
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}
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/*
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* Atomically swap the contents of a register with memory. Should be atomic
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* between multiple CPU's and within interrupts on the same CPU.
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*/
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#define arch_xchg(ptr, v) ((__typeof__(*(ptr)))__arch_xchg((unsigned long)(v), (ptr), \
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sizeof(*(ptr))))
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/*
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* see rt-mutex-design.txt; cmpxchg supposedly checks if *ptr == A and swaps.
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* looks just like atomic_cmpxchg on our arch currently with a bunch of
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* variable casting.
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*/
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#define arch_cmpxchg(ptr, old, new) \
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({ \
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__typeof__(ptr) __ptr = (ptr); \
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__typeof__(*(ptr)) __old = (old); \
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__typeof__(*(ptr)) __new = (new); \
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__typeof__(*(ptr)) __oldval = (__typeof__(*(ptr))) 0; \
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\
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asm volatile( \
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"1: %0 = memw_locked(%1);\n" \
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" { P0 = cmp.eq(%0,%2);\n" \
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" if (!P0.new) jump:nt 2f; }\n" \
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" memw_locked(%1,p0) = %3;\n" \
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" if (!P0) jump 1b;\n" \
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"2:\n" \
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: "=&r" (__oldval) \
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: "r" (__ptr), "r" (__old), "r" (__new) \
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: "memory", "p0" \
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); \
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__oldval; \
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})
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#endif /* _ASM_CMPXCHG_H */
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