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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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13e248aab7
In preparation for handling cache maintenance of guest pages from within the pKVM hypervisor at EL2, introduce an EL2 copy of icache_inval_pou() which will later be plumbed into the stage-2 page-table cache maintenance callbacks, ensuring that the initial contents of pages mapped as executable into the guest stage-2 page-table is visible to the instruction fetcher. Tested-by: Vincent Donnefort <vdonnefort@google.com> Signed-off-by: Will Deacon <will@kernel.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20221110190259.26861-17-will@kernel.org
26 lines
634 B
ArmAsm
26 lines
634 B
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Code copied from arch/arm64/mm/cache.S.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/alternative.h>
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SYM_FUNC_START(__pi_dcache_clean_inval_poc)
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dcache_by_line_op civac, sy, x0, x1, x2, x3
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ret
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SYM_FUNC_END(__pi_dcache_clean_inval_poc)
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SYM_FUNC_ALIAS(dcache_clean_inval_poc, __pi_dcache_clean_inval_poc)
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SYM_FUNC_START(__pi_icache_inval_pou)
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alternative_if ARM64_HAS_CACHE_DIC
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isb
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ret
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alternative_else_nop_endif
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invalidate_icache_by_line x0, x1, x2, x3
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ret
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SYM_FUNC_END(__pi_icache_inval_pou)
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SYM_FUNC_ALIAS(icache_inval_pou, __pi_icache_inval_pou)
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