mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-04 18:49:41 +00:00
17efc1acee
The KVM PV ABI recently added a feature that allows the VM to discover
the set of physical CPU implementations, identified by a tuple of
{MIDR_EL1, REVIDR_EL1, AIDR_EL1}. Unlike other KVM PV features, the
expectation is that the VMM implements the hypercall instead of KVM as
it has the authoritative view of where the VM gets scheduled.
To do this the VMM needs to know the values of these registers on any
CPU in the system. While MIDR_EL1 and REVIDR_EL1 are already exposed,
AIDR_EL1 is not. Provide it in sysfs along with the other identification
registers.
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
Link: https://lore.kernel.org/r/20250403231626.3181116-1-oliver.upton@linux.dev
Signed-off-by: Will Deacon <will@kernel.org>
83 lines
1.6 KiB
C
83 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2014 ARM Ltd.
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*/
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#ifndef __ASM_CPU_H
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#define __ASM_CPU_H
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#include <linux/cpu.h>
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#include <linux/init.h>
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#include <linux/percpu.h>
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/*
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* Records attributes of an individual CPU.
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*/
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struct cpuinfo_32bit {
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u32 reg_id_dfr0;
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u32 reg_id_dfr1;
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u32 reg_id_isar0;
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u32 reg_id_isar1;
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u32 reg_id_isar2;
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u32 reg_id_isar3;
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u32 reg_id_isar4;
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u32 reg_id_isar5;
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u32 reg_id_isar6;
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u32 reg_id_mmfr0;
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u32 reg_id_mmfr1;
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u32 reg_id_mmfr2;
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u32 reg_id_mmfr3;
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u32 reg_id_mmfr4;
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u32 reg_id_mmfr5;
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u32 reg_id_pfr0;
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u32 reg_id_pfr1;
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u32 reg_id_pfr2;
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u32 reg_mvfr0;
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u32 reg_mvfr1;
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u32 reg_mvfr2;
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};
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struct cpuinfo_arm64 {
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struct kobject kobj;
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u64 reg_ctr;
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u64 reg_cntfrq;
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u64 reg_dczid;
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u64 reg_midr;
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u64 reg_revidr;
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u64 reg_aidr;
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u64 reg_gmid;
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u64 reg_smidr;
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u64 reg_mpamidr;
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u64 reg_id_aa64dfr0;
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u64 reg_id_aa64dfr1;
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u64 reg_id_aa64isar0;
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u64 reg_id_aa64isar1;
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u64 reg_id_aa64isar2;
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u64 reg_id_aa64isar3;
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u64 reg_id_aa64mmfr0;
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u64 reg_id_aa64mmfr1;
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u64 reg_id_aa64mmfr2;
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u64 reg_id_aa64mmfr3;
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u64 reg_id_aa64mmfr4;
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u64 reg_id_aa64pfr0;
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u64 reg_id_aa64pfr1;
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u64 reg_id_aa64pfr2;
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u64 reg_id_aa64zfr0;
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u64 reg_id_aa64smfr0;
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u64 reg_id_aa64fpfr0;
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struct cpuinfo_32bit aarch32;
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};
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DECLARE_PER_CPU(struct cpuinfo_arm64, cpu_data);
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void cpuinfo_store_cpu(void);
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void __init cpuinfo_store_boot_cpu(void);
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void __init init_cpu_features(struct cpuinfo_arm64 *info);
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void update_cpu_features(int cpu, struct cpuinfo_arm64 *info,
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struct cpuinfo_arm64 *boot);
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#endif /* __ASM_CPU_H */
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