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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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2da2ac3c8d
All zynqmp boards have been already described via mdio node that's why also convert zc1751. With using mdio node there is an option to add reset property for the whole mdio bus. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/dc228a27579b48f3e768fcb439d118b4a0f0ef5b.1695040866.git.michal.simek@amd.com
202 lines
3.2 KiB
Plaintext
202 lines
3.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* dts file for Xilinx ZynqMP zc1751-xm017-dc3
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*
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* (C) Copyright 2016 - 2021, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@amd.com>
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*/
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/dts-v1/;
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#include "zynqmp.dtsi"
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#include "zynqmp-clk-ccf.dtsi"
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#include <dt-bindings/phy/phy.h>
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/ {
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model = "ZynqMP zc1751-xm017-dc3 RevA";
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compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
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aliases {
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ethernet0 = &gem0;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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mmc0 = &sdhci1;
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rtc0 = &rtc;
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serial0 = &uart0;
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serial1 = &uart1;
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usb0 = &usb0;
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usb1 = &usb1;
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};
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chosen {
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bootargs = "earlycon";
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
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};
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clock_si5338_2: clk26 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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};
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clock_si5338_3: clk125 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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};
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};
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&fpd_dma_chan1 {
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status = "okay";
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};
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&fpd_dma_chan2 {
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status = "okay";
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};
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&fpd_dma_chan3 {
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status = "okay";
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};
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&fpd_dma_chan4 {
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status = "okay";
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};
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&fpd_dma_chan5 {
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status = "okay";
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};
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&fpd_dma_chan6 {
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status = "okay";
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};
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&fpd_dma_chan7 {
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status = "okay";
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};
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&fpd_dma_chan8 {
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status = "okay";
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};
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&gem0 {
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status = "okay";
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phy-handle = <&phy0>;
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phy-mode = "rgmii-id";
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mdio: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@0 { /* VSC8211 */
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reg = <0>;
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};
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};
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};
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&gpio {
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status = "okay";
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};
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/* just eeprom here */
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&i2c0 {
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status = "okay";
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clock-frequency = <400000>;
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tca6416_u26: gpio@20 {
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compatible = "ti,tca6416";
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reg = <0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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/* IRQ not connected */
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};
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rtc@68 {
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compatible = "dallas,ds1339";
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reg = <0x68>;
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};
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};
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/* eeprom24c02 and SE98A temp chip pca9306 */
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&i2c1 {
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status = "okay";
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clock-frequency = <400000>;
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};
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/* MT29F64G08AECDBJ4-6 */
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&nand0 {
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status = "okay";
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arasan,has-mdma;
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num-cs = <2>;
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};
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&psgtr {
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status = "okay";
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/* usb3, sata */
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clocks = <&clock_si5338_2>, <&clock_si5338_3>;
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clock-names = "ref2", "ref3";
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};
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&rtc {
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status = "okay";
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};
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&sata {
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status = "okay";
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/* SATA phy OOB timing settings */
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ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
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ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
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ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
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ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
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ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
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ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
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ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
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ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
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phy-names = "sata-phy";
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phys = <&psgtr 2 PHY_TYPE_SATA 0 3>;
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};
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&sdhci1 { /* emmc with some settings */
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status = "okay";
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};
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/* main */
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&uart0 {
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status = "okay";
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};
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/* DB9 */
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&uart1 {
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status = "okay";
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};
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&usb0 {
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status = "okay";
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phy-names = "usb3-phy";
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phys = <&psgtr 0 PHY_TYPE_USB3 0 2>;
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};
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&dwc3_0 {
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status = "okay";
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dr_mode = "host";
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snps,usb3_lpm_capable;
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maximum-speed = "super-speed";
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};
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/* ULPI SMSC USB3320 */
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&usb1 {
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status = "okay";
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phy-names = "usb3-phy";
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phys = <&psgtr 3 PHY_TYPE_USB3 1 2>;
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};
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&dwc3_1 {
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status = "okay";
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dr_mode = "host";
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snps,usb3_lpm_capable;
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maximum-speed = "super-speed";
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};
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