mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-02 08:32:55 +00:00
ebeab0be70
The FSD SoC contains two instances of Synopsys DWC QoS Ethernet IP, one in FSYS0 block and other in PERIC block. The ethernet interface is connected to a switch which is not managed by Linux. Adds device tree node for Ethernet in PERIC Block and enables the same for FSD platform. Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Jayati Sahu <jayati.sahu@samsung.com> Signed-off-by: Swathi K S <swathi.ks@samsung.com> Link: https://lore.kernel.org/r/20250307044904.59077-3-swathi.ks@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
1064 lines
32 KiB
Plaintext
1064 lines
32 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Tesla Full Self-Driving SoC device tree source
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*
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* Copyright (c) 2017-2022 Samsung Electronics Co., Ltd.
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* https://www.samsung.com
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* Copyright (c) 2017-2022 Tesla, Inc.
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* https://www.tesla.com
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*/
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#include <dt-bindings/clock/fsd-clk.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "tesla,fsd";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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i2c0 = &hsi2c_0;
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i2c1 = &hsi2c_1;
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i2c2 = &hsi2c_2;
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i2c3 = &hsi2c_3;
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i2c4 = &hsi2c_4;
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i2c5 = &hsi2c_5;
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i2c6 = &hsi2c_6;
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i2c7 = &hsi2c_7;
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pinctrl0 = &pinctrl_fsys0;
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pinctrl1 = &pinctrl_peric;
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pinctrl2 = &pinctrl_pmu;
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spi0 = &spi_0;
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spi1 = &spi_1;
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spi2 = &spi_2;
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpucl0_0>;
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};
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core1 {
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cpu = <&cpucl0_1>;
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};
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core2 {
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cpu = <&cpucl0_2>;
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};
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core3 {
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cpu = <&cpucl0_3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpucl1_0>;
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};
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core1 {
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cpu = <&cpucl1_1>;
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};
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core2 {
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cpu = <&cpucl1_2>;
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};
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core3 {
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cpu = <&cpucl1_3>;
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};
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};
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cluster2 {
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core0 {
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cpu = <&cpucl2_0>;
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};
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core1 {
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cpu = <&cpucl2_1>;
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};
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core2 {
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cpu = <&cpucl2_2>;
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};
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core3 {
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cpu = <&cpucl2_3>;
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};
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};
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};
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/* Cluster 0 */
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cpucl0_0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x0 0x000>;
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enable-method = "psci";
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clock-frequency = <2400000000>;
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cpu-idle-states = <&cpu_sleep>;
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&cpucl_l2>;
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};
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cpucl0_1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x0 0x001>;
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enable-method = "psci";
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clock-frequency = <2400000000>;
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cpu-idle-states = <&cpu_sleep>;
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&cpucl_l2>;
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};
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cpucl0_2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x0 0x002>;
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enable-method = "psci";
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clock-frequency = <2400000000>;
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cpu-idle-states = <&cpu_sleep>;
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&cpucl_l2>;
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};
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cpucl0_3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x0 0x003>;
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enable-method = "psci";
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cpu-idle-states = <&cpu_sleep>;
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&cpucl_l2>;
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};
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/* Cluster 1 */
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cpucl1_0: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x0 0x100>;
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enable-method = "psci";
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clock-frequency = <2400000000>;
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cpu-idle-states = <&cpu_sleep>;
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&cpucl_l2>;
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};
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cpucl1_1: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x0 0x101>;
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enable-method = "psci";
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clock-frequency = <2400000000>;
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cpu-idle-states = <&cpu_sleep>;
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&cpucl_l2>;
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};
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cpucl1_2: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x0 0x102>;
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enable-method = "psci";
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clock-frequency = <2400000000>;
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cpu-idle-states = <&cpu_sleep>;
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&cpucl_l2>;
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};
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cpucl1_3: cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x0 0x103>;
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enable-method = "psci";
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clock-frequency = <2400000000>;
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cpu-idle-states = <&cpu_sleep>;
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&cpucl_l2>;
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};
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/* Cluster 2 */
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cpucl2_0: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x0 0x200>;
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enable-method = "psci";
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clock-frequency = <2400000000>;
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cpu-idle-states = <&cpu_sleep>;
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&cpucl_l2>;
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};
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cpucl2_1: cpu@201 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x0 0x201>;
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enable-method = "psci";
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clock-frequency = <2400000000>;
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cpu-idle-states = <&cpu_sleep>;
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&cpucl_l2>;
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};
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cpucl2_2: cpu@202 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x0 0x202>;
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enable-method = "psci";
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clock-frequency = <2400000000>;
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cpu-idle-states = <&cpu_sleep>;
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&cpucl_l2>;
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};
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cpucl2_3: cpu@203 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x0 0x203>;
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enable-method = "psci";
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clock-frequency = <2400000000>;
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cpu-idle-states = <&cpu_sleep>;
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&cpucl_l2>;
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};
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cpucl_l2: l2-cache0 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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cache-size = <0x400000>;
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cache-line-size = <64>;
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cache-sets = <4096>;
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};
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idle-states {
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entry-method = "psci";
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cpu_sleep: cpu-sleep {
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idle-state-name = "c2";
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compatible = "arm,idle-state";
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local-timer-stop;
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arm,psci-suspend-param = <0x0010000>;
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entry-latency-us = <30>;
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exit-latency-us = <75>;
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min-residency-us = <300>;
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};
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};
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};
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arm-pmu {
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compatible = "arm,cortex-a72-pmu";
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interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpucl0_0>, <&cpucl0_1>, <&cpucl0_2>,
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<&cpucl0_3>, <&cpucl1_0>, <&cpucl1_1>,
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<&cpucl1_2>, <&cpucl1_3>, <&cpucl2_0>,
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<&cpucl2_1>, <&cpucl2_2>, <&cpucl2_3>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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fin_pll: clock {
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compatible = "fixed-clock";
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clock-output-names = "fin_pll";
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#clock-cells = <0>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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mfc_left: region@84000000 {
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compatible = "shared-dma-pool";
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no-map;
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reg = <0 0x84000000 0 0x8000000>;
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};
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};
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soc: soc@0 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0x0 0x0 0x18000000>;
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dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
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gic: interrupt-controller@10400000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x0 0x10400000 0x0 0x10000>, /* GICD */
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<0x0 0x10600000 0x0 0x200000>; /* GICR_RD+GICR_SGI */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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smmu_imem: iommu@10200000 {
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compatible = "arm,mmu-500";
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reg = <0x0 0x10200000 0x0 0x10000>;
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#iommu-cells = <2>;
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#global-interrupts = <7>;
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interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */
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<GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
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<GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */
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<GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
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/* Performance counter interrupts */
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<GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, /* for FSYS1_0 */
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<GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, /* for FSYS1_1 */
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<GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, /* for IMEM_0 */
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/* Per context non-secure context interrupts, 0-3 interrupts */
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<GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */
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<GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_1 */
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<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_2 */
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<GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_3 */
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};
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smmu_isp: iommu@12100000 {
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compatible = "arm,mmu-500";
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reg = <0x0 0x12100000 0x0 0x10000>;
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#iommu-cells = <2>;
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#global-interrupts = <11>;
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interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */
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<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
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<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */
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<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
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/* Performance counter interrupts */
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<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_CSI */
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<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_DP_0 */
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<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_DP_1 */
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<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_ISP_0 */
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<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_ISP_1 */
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<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_MFC_0 */
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<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_MFC_1 */
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/* Per context non-secure context interrupts, 0-7 interrupts */
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<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */
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<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_1 */
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<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_2 */
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<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_3 */
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<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_4 */
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<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_5 */
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<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_6 */
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<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_7 */
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};
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smmu_peric: iommu@14900000 {
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compatible = "arm,mmu-500";
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reg = <0x0 0x14900000 0x0 0x10000>;
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#iommu-cells = <2>;
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#global-interrupts = <5>;
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interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */
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<GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
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<GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */
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<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
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/* Performance counter interrupts */
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<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, /* for PERIC */
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/* Per context non-secure context interrupts, 0-1 interrupts */
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<GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */
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<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_1 */
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};
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smmu_fsys0: iommu@15450000 {
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compatible = "arm,mmu-500";
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reg = <0x0 0x15450000 0x0 0x10000>;
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#iommu-cells = <2>;
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#global-interrupts = <5>;
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interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */
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<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
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<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */
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<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
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/* Performance counter interrupts */
|
|
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, /* for FSYS0 */
|
|
/* Per context non-secure context interrupts, 0-1 interrupts */
|
|
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */
|
|
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_1 */
|
|
};
|
|
|
|
clock_imem: clock-controller@10010000 {
|
|
compatible = "tesla,fsd-clock-imem";
|
|
reg = <0x0 0x10010000 0x0 0x3000>;
|
|
#clock-cells = <1>;
|
|
clocks = <&fin_pll>,
|
|
<&clock_cmu DOUT_CMU_IMEM_TCUCLK>,
|
|
<&clock_cmu DOUT_CMU_IMEM_ACLK>,
|
|
<&clock_cmu DOUT_CMU_IMEM_DMACLK>;
|
|
clock-names = "fin_pll",
|
|
"dout_cmu_imem_tcuclk",
|
|
"dout_cmu_imem_aclk",
|
|
"dout_cmu_imem_dmaclk";
|
|
};
|
|
|
|
clock_cmu: clock-controller@11c10000 {
|
|
compatible = "tesla,fsd-clock-cmu";
|
|
reg = <0x0 0x11c10000 0x0 0x3000>;
|
|
#clock-cells = <1>;
|
|
clocks = <&fin_pll>;
|
|
clock-names = "fin_pll";
|
|
};
|
|
|
|
clock_csi: clock-controller@12610000 {
|
|
compatible = "tesla,fsd-clock-cam_csi";
|
|
reg = <0x0 0x12610000 0x0 0x3000>;
|
|
#clock-cells = <1>;
|
|
clocks = <&fin_pll>;
|
|
clock-names = "fin_pll";
|
|
};
|
|
|
|
sysreg_cam: system-controller@12630000 {
|
|
compatible = "tesla,fsd-cam-sysreg", "syscon";
|
|
reg = <0x0 0x12630000 0x0 0x500>;
|
|
};
|
|
|
|
clock_mfc: clock-controller@12810000 {
|
|
compatible = "tesla,fsd-clock-mfc";
|
|
reg = <0x0 0x12810000 0x0 0x3000>;
|
|
#clock-cells = <1>;
|
|
clocks = <&fin_pll>;
|
|
clock-names = "fin_pll";
|
|
};
|
|
|
|
clock_peric: clock-controller@14010000 {
|
|
compatible = "tesla,fsd-clock-peric";
|
|
reg = <0x0 0x14010000 0x0 0x3000>;
|
|
#clock-cells = <1>;
|
|
clocks = <&fin_pll>,
|
|
<&clock_cmu DOUT_CMU_PLL_SHARED0_DIV4>,
|
|
<&clock_cmu DOUT_CMU_PERIC_SHARED1DIV36>,
|
|
<&clock_cmu DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK>,
|
|
<&clock_cmu DOUT_CMU_PERIC_SHARED0DIV20>,
|
|
<&clock_cmu DOUT_CMU_PERIC_SHARED1DIV4_DMACLK>;
|
|
clock-names = "fin_pll",
|
|
"dout_cmu_pll_shared0_div4",
|
|
"dout_cmu_peric_shared1div36",
|
|
"dout_cmu_peric_shared0div3_tbuclk",
|
|
"dout_cmu_peric_shared0div20",
|
|
"dout_cmu_peric_shared1div4_dmaclk";
|
|
};
|
|
|
|
sysreg_peric: system-controller@14030000 {
|
|
compatible = "tesla,fsd-peric-sysreg", "syscon";
|
|
reg = <0x0 0x14030000 0x0 0x1000>;
|
|
};
|
|
|
|
clock_fsys0: clock-controller@15010000 {
|
|
compatible = "tesla,fsd-clock-fsys0";
|
|
reg = <0x0 0x15010000 0x0 0x3000>;
|
|
#clock-cells = <1>;
|
|
clocks = <&fin_pll>,
|
|
<&clock_cmu DOUT_CMU_PLL_SHARED0_DIV6>,
|
|
<&clock_cmu DOUT_CMU_FSYS0_SHARED1DIV4>,
|
|
<&clock_cmu DOUT_CMU_FSYS0_SHARED0DIV4>;
|
|
clock-names = "fin_pll",
|
|
"dout_cmu_pll_shared0_div6",
|
|
"dout_cmu_fsys0_shared1div4",
|
|
"dout_cmu_fsys0_shared0div4";
|
|
};
|
|
|
|
sysreg_fsys0: system-controller@15030000 {
|
|
compatible = "tesla,fsd-fsys0-sysreg", "syscon";
|
|
reg = <0x0 0x15030000 0x0 0x1000>;
|
|
};
|
|
|
|
clock_fsys1: clock-controller@16810000 {
|
|
compatible = "tesla,fsd-clock-fsys1";
|
|
reg = <0x0 0x16810000 0x0 0x3000>;
|
|
#clock-cells = <1>;
|
|
clocks = <&fin_pll>,
|
|
<&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV8>,
|
|
<&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV4>;
|
|
clock-names = "fin_pll",
|
|
"dout_cmu_fsys1_shared0div8",
|
|
"dout_cmu_fsys1_shared0div4";
|
|
};
|
|
|
|
sysreg_fsys1: system-controller@16830000 {
|
|
compatible = "tesla,fsd-fsys1-sysreg", "syscon";
|
|
reg = <0x0 0x16830000 0x0 0x1000>;
|
|
};
|
|
|
|
mdma0: dma-controller@10100000 {
|
|
compatible = "arm,pl330", "arm,primecell";
|
|
reg = <0x0 0x10100000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
|
|
#dma-cells = <1>;
|
|
clocks = <&clock_imem IMEM_DMA0_IPCLKPORT_ACLK>;
|
|
clock-names = "apb_pclk";
|
|
iommus = <&smmu_imem 0x800 0x0>;
|
|
};
|
|
|
|
mdma1: dma-controller@10110000 {
|
|
compatible = "arm,pl330", "arm,primecell";
|
|
reg = <0x0 0x10110000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
|
|
#dma-cells = <1>;
|
|
clocks = <&clock_imem IMEM_DMA1_IPCLKPORT_ACLK>;
|
|
clock-names = "apb_pclk";
|
|
iommus = <&smmu_imem 0x801 0x0>;
|
|
};
|
|
|
|
pdma0: dma-controller@14280000 {
|
|
compatible = "arm,pl330", "arm,primecell";
|
|
reg = <0x0 0x14280000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
|
|
#dma-cells = <1>;
|
|
clocks = <&clock_peric PERIC_DMA0_IPCLKPORT_ACLK>;
|
|
clock-names = "apb_pclk";
|
|
iommus = <&smmu_peric 0x2 0x0>;
|
|
};
|
|
|
|
pdma1: dma-controller@14290000 {
|
|
compatible = "arm,pl330", "arm,primecell";
|
|
reg = <0x0 0x14290000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
|
|
#dma-cells = <1>;
|
|
clocks = <&clock_peric PERIC_DMA1_IPCLKPORT_ACLK>;
|
|
clock-names = "apb_pclk";
|
|
iommus = <&smmu_peric 0x1 0x0>;
|
|
};
|
|
|
|
serial_0: serial@14180000 {
|
|
compatible = "tesla,fsd-uart", "samsung,exynos4210-uart";
|
|
reg = <0x0 0x14180000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&pdma1 1>, <&pdma1 0>;
|
|
dma-names = "rx", "tx";
|
|
clocks = <&clock_peric PERIC_PCLK_UART0>,
|
|
<&clock_peric PERIC_SCLK_UART0>;
|
|
clock-names = "uart", "clk_uart_baud0";
|
|
samsung,uart-fifosize = <64>;
|
|
status = "disabled";
|
|
};
|
|
|
|
serial_1: serial@14190000 {
|
|
compatible = "tesla,fsd-uart", "samsung,exynos4210-uart";
|
|
reg = <0x0 0x14190000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&pdma1 3>, <&pdma1 2>;
|
|
dma-names = "rx", "tx";
|
|
clocks = <&clock_peric PERIC_PCLK_UART1>,
|
|
<&clock_peric PERIC_SCLK_UART1>;
|
|
clock-names = "uart", "clk_uart_baud0";
|
|
samsung,uart-fifosize = <64>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pmu_system_controller: system-controller@11400000 {
|
|
compatible = "tesla,fsd-pmu", "samsung,exynos7-pmu", "syscon";
|
|
reg = <0x0 0x11400000 0x0 0x5000>;
|
|
};
|
|
|
|
watchdog_0: watchdog@100a0000 {
|
|
compatible = "tesla,fsd-wdt", "samsung,exynos7-wdt";
|
|
reg = <0x0 0x100a0000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>;
|
|
samsung,syscon-phandle = <&pmu_system_controller>;
|
|
clocks = <&fin_pll>;
|
|
clock-names = "watchdog";
|
|
};
|
|
|
|
watchdog_1: watchdog@100b0000 {
|
|
compatible = "tesla,fsd-wdt", "samsung,exynos7-wdt";
|
|
reg = <0x0 0x100b0000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
|
|
samsung,syscon-phandle = <&pmu_system_controller>;
|
|
clocks = <&fin_pll>;
|
|
clock-names = "watchdog";
|
|
};
|
|
|
|
watchdog_2: watchdog@100c0000 {
|
|
compatible = "tesla,fsd-wdt", "samsung,exynos7-wdt";
|
|
reg = <0x0 0x100c0000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
|
|
samsung,syscon-phandle = <&pmu_system_controller>;
|
|
clocks = <&fin_pll>;
|
|
clock-names = "watchdog";
|
|
};
|
|
|
|
pwm_0: pwm@14100000 {
|
|
compatible = "tesla,fsd-pwm", "samsung,exynos4210-pwm";
|
|
reg = <0x0 0x14100000 0x0 0x100>;
|
|
samsung,pwm-outputs = <0>, <1>, <2>, <3>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&clock_peric PERIC_PWM0_IPCLKPORT_I_PCLK_S0>;
|
|
clock-names = "timers";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm_1: pwm@14110000 {
|
|
compatible = "tesla,fsd-pwm", "samsung,exynos4210-pwm";
|
|
reg = <0x0 0x14110000 0x0 0x100>;
|
|
samsung,pwm-outputs = <0>, <1>, <2>, <3>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&clock_peric PERIC_PWM1_IPCLKPORT_I_PCLK_S0>;
|
|
clock-names = "timers";
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_0: i2c@14200000 {
|
|
compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c";
|
|
reg = <0x0 0x14200000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&hs_i2c0_bus>;
|
|
clocks = <&clock_peric PERIC_PCLK_HSI2C0>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_1: i2c@14210000 {
|
|
compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c";
|
|
reg = <0x0 0x14210000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&hs_i2c1_bus>;
|
|
clocks = <&clock_peric PERIC_PCLK_HSI2C1>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_2: i2c@14220000 {
|
|
compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c";
|
|
reg = <0x0 0x14220000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&hs_i2c2_bus>;
|
|
clocks = <&clock_peric PERIC_PCLK_HSI2C2>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_3: i2c@14230000 {
|
|
compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c";
|
|
reg = <0x0 0x14230000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&hs_i2c3_bus>;
|
|
clocks = <&clock_peric PERIC_PCLK_HSI2C3>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_4: i2c@14240000 {
|
|
compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c";
|
|
reg = <0x0 0x14240000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&hs_i2c4_bus>;
|
|
clocks = <&clock_peric PERIC_PCLK_HSI2C4>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_5: i2c@14250000 {
|
|
compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c";
|
|
reg = <0x0 0x14250000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&hs_i2c5_bus>;
|
|
clocks = <&clock_peric PERIC_PCLK_HSI2C5>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_6: i2c@14260000 {
|
|
compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c";
|
|
reg = <0x0 0x14260000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&hs_i2c6_bus>;
|
|
clocks = <&clock_peric PERIC_PCLK_HSI2C6>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_7: i2c@14270000 {
|
|
compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c";
|
|
reg = <0x0 0x14270000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&hs_i2c7_bus>;
|
|
clocks = <&clock_peric PERIC_PCLK_HSI2C7>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2s_0: i2s@140e0000 {
|
|
compatible = "tesla,fsd-i2s";
|
|
reg = <0x0 0x140e0000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&pdma1 14>, <&pdma1 13>, <&pdma1 12>;
|
|
dma-names = "tx", "rx", "tx-sec";
|
|
#clock-cells = <1>;
|
|
clocks = <&clock_peric PERIC_PCLK_TDM0>,
|
|
<&clock_peric PERIC_HCLK_TDM0>,
|
|
<&clock_peric PERIC_HCLK_TDM0>;
|
|
clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2s0_bus>;
|
|
#sound-dai-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2s_1: i2s@140f0000 {
|
|
compatible = "tesla,fsd-i2s";
|
|
reg = <0x0 0x140f0000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&pdma1 17>, <&pdma1 16>, <&pdma1 15>;
|
|
dma-names = "tx", "rx", "tx-sec";
|
|
#clock-cells = <1>;
|
|
clocks = <&clock_peric PERIC_PCLK_TDM1>,
|
|
<&clock_peric PERIC_HCLK_TDM1>,
|
|
<&clock_peric PERIC_HCLK_TDM1>;
|
|
clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2s1_bus>;
|
|
#sound-dai-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pinctrl_pmu: pinctrl@114f0000 {
|
|
compatible = "tesla,fsd-pinctrl";
|
|
reg = <0x0 0x114f0000 0x0 0x1000>;
|
|
};
|
|
|
|
pinctrl_peric: pinctrl@141f0000 {
|
|
compatible = "tesla,fsd-pinctrl";
|
|
reg = <0x0 0x141f0000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
pinctrl_fsys0: pinctrl@15020000 {
|
|
compatible = "tesla,fsd-pinctrl";
|
|
reg = <0x0 0x15020000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
m_can0: can@14088000 {
|
|
compatible = "bosch,m_can";
|
|
reg = <0x0 0x14088000 0x0 0x0200>,
|
|
<0x0 0x14080000 0x0 0x8000>;
|
|
reg-names = "m_can", "message_ram";
|
|
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "int0", "int1";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&m_can0_bus>;
|
|
clocks = <&clock_peric PERIC_MCAN0_IPCLKPORT_PCLK>,
|
|
<&clock_peric PERIC_MCAN0_IPCLKPORT_CCLK>;
|
|
clock-names = "hclk", "cclk";
|
|
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
|
|
status = "disabled";
|
|
};
|
|
|
|
m_can1: can@14098000 {
|
|
compatible = "bosch,m_can";
|
|
reg = <0x0 0x14098000 0x0 0x0200>,
|
|
<0x0 0x14090000 0x0 0x8000>;
|
|
reg-names = "m_can", "message_ram";
|
|
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "int0", "int1";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&m_can1_bus>;
|
|
clocks = <&clock_peric PERIC_MCAN1_IPCLKPORT_PCLK>,
|
|
<&clock_peric PERIC_MCAN1_IPCLKPORT_CCLK>;
|
|
clock-names = "hclk", "cclk";
|
|
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
|
|
status = "disabled";
|
|
};
|
|
|
|
m_can2: can@140a8000 {
|
|
compatible = "bosch,m_can";
|
|
reg = <0x0 0x140a8000 0x0 0x0200>,
|
|
<0x0 0x140a0000 0x0 0x8000>;
|
|
reg-names = "m_can", "message_ram";
|
|
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "int0", "int1";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&m_can2_bus>;
|
|
clocks = <&clock_peric PERIC_MCAN2_IPCLKPORT_PCLK>,
|
|
<&clock_peric PERIC_MCAN2_IPCLKPORT_CCLK>;
|
|
clock-names = "hclk", "cclk";
|
|
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
|
|
status = "disabled";
|
|
};
|
|
|
|
m_can3: can@140b8000 {
|
|
compatible = "bosch,m_can";
|
|
reg = <0x0 0x140b8000 0x0 0x0200>,
|
|
<0x0 0x140b0000 0x0 0x8000>;
|
|
reg-names = "m_can", "message_ram";
|
|
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "int0", "int1";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&m_can3_bus>;
|
|
clocks = <&clock_peric PERIC_MCAN3_IPCLKPORT_PCLK>,
|
|
<&clock_peric PERIC_MCAN3_IPCLKPORT_CCLK>;
|
|
clock-names = "hclk", "cclk";
|
|
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi_0: spi@14140000 {
|
|
compatible = "tesla,fsd-spi";
|
|
reg = <0x0 0x14140000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&pdma1 4>, <&pdma1 5>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clock_peric PERIC_PCLK_SPI0>,
|
|
<&clock_peric PERIC_SCLK_SPI0>;
|
|
clock-names = "spi", "spi_busclk0";
|
|
samsung,spi-src-clk = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi0_bus>;
|
|
num-cs = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi_1: spi@14150000 {
|
|
compatible = "tesla,fsd-spi";
|
|
reg = <0x0 0x14150000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&pdma1 6>, <&pdma1 7>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clock_peric PERIC_PCLK_SPI1>,
|
|
<&clock_peric PERIC_SCLK_SPI1>;
|
|
clock-names = "spi", "spi_busclk0";
|
|
samsung,spi-src-clk = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi1_bus>;
|
|
num-cs = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi_2: spi@14160000 {
|
|
compatible = "tesla,fsd-spi";
|
|
reg = <0x0 0x14160000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&pdma1 8>, <&pdma1 9>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clock_peric PERIC_PCLK_SPI2>,
|
|
<&clock_peric PERIC_SCLK_SPI2>;
|
|
clock-names = "spi", "spi_busclk0";
|
|
samsung,spi-src-clk = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi2_bus>;
|
|
num-cs = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
timer@10040000 {
|
|
compatible = "tesla,fsd-mct", "samsung,exynos4210-mct";
|
|
reg = <0x0 0x10040000 0x0 0x800>;
|
|
interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&fin_pll>, <&clock_imem IMEM_MCT_PCLK>;
|
|
clock-names = "fin_pll", "mct";
|
|
};
|
|
|
|
mfc: mfc@12880000 {
|
|
compatible = "tesla,fsd-mfc";
|
|
reg = <0x0 0x12880000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "mfc";
|
|
clocks = <&clock_mfc MFC_MFC_IPCLKPORT_ACLK>;
|
|
memory-region = <&mfc_left>;
|
|
};
|
|
|
|
ethernet1: ethernet@14300000 {
|
|
compatible = "tesla,fsd-ethqos";
|
|
reg = <0x0 0x14300000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "macirq";
|
|
clocks = <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I>,
|
|
<&clock_peric PERIC_EQOS_TOP_IPCLKPORT_ACLK_I>,
|
|
<&clock_peric PERIC_EQOS_TOP_IPCLKPORT_HCLK_I>,
|
|
<&clock_peric PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I>,
|
|
<&clock_peric PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I>,
|
|
<&clock_peric PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK>,
|
|
<&clock_peric PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK>,
|
|
<&clock_peric PERIC_EQOS_PHYRXCLK_MUX>,
|
|
<&clock_peric PERIC_EQOS_PHYRXCLK>,
|
|
<&clock_peric PERIC_DOUT_RGMII_CLK>;
|
|
clock-names = "ptp_ref", "master_bus", "slave_bus", "tx", "rx",
|
|
"master2_bus", "slave2_bus", "eqos_rxclk_mux",
|
|
"eqos_phyrxclk", "dout_peric_rgmii_clk";
|
|
assigned-clocks = <&clock_peric PERIC_EQOS_PHYRXCLK_MUX>,
|
|
<&clock_peric PERIC_EQOS_PHYRXCLK>;
|
|
assigned-clock-parents = <&clock_peric PERIC_EQOS_PHYRXCLK>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <ð1_tx_clk>, <ð1_tx_data>, <ð1_tx_ctrl>,
|
|
<ð1_phy_intr>, <ð1_rx_clk>, <ð1_rx_data>,
|
|
<ð1_rx_ctrl>, <ð1_mdio>;
|
|
local-mac-address = [00 00 00 00 00 00];
|
|
iommus = <&smmu_peric 0x0 0x1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ufs: ufs@15120000 {
|
|
compatible = "tesla,fsd-ufs";
|
|
reg = <0x0 0x15120000 0x0 0x200>, /* 0: HCI standard */
|
|
<0x0 0x15121100 0x0 0x200>, /* 1: Vendor specified */
|
|
<0x0 0x15110000 0x0 0x8000>, /* 2: UNIPRO */
|
|
<0x0 0x15130000 0x0 0x100>; /* 3: UFS protector */
|
|
reg-names = "hci", "vs_hci", "unipro", "ufsp";
|
|
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clock_fsys0 UFS0_TOP0_HCLK_BUS>,
|
|
<&clock_fsys0 UFS0_TOP0_CLK_UNIPRO>;
|
|
clock-names = "core_clk", "sclk_unipro_main";
|
|
freq-table-hz = <0 0>, <0 0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
|
|
phys = <&ufs_phy>;
|
|
phy-names = "ufs-phy";
|
|
status = "disabled";
|
|
};
|
|
|
|
ufs_phy: ufs-phy@15124000 {
|
|
compatible = "tesla,fsd-ufs-phy";
|
|
reg = <0x0 0x15124000 0x0 0x800>;
|
|
reg-names = "phy-pma";
|
|
samsung,pmu-syscon = <&pmu_system_controller>;
|
|
#phy-cells = <0>;
|
|
clocks = <&clock_fsys0 UFS0_MPHY_REFCLK_IXTAL26>;
|
|
clock-names = "ref_clk";
|
|
};
|
|
|
|
ethernet0: ethernet@15300000 {
|
|
compatible = "tesla,fsd-ethqos";
|
|
reg = <0x0 0x15300000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "macirq";
|
|
clocks = <&clock_fsys0 FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I>,
|
|
<&clock_fsys0 FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I>,
|
|
<&clock_fsys0 FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I>,
|
|
<&clock_fsys0 FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I>,
|
|
<&clock_fsys0 FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I>;
|
|
clock-names = "ptp_ref", "master_bus", "slave_bus", "tx", "rx";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <ð0_tx_clk>, <ð0_tx_data>, <ð0_tx_ctrl>,
|
|
<ð0_phy_intr>, <ð0_rx_clk>, <ð0_rx_data>,
|
|
<ð0_rx_ctrl>, <ð0_mdio>;
|
|
local-mac-address = [00 00 00 00 00 00];
|
|
iommus = <&smmu_fsys0 0x0 0x1>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
|
|
#include "fsd-pinctrl.dtsi"
|